Transcript No Slide Title

Chapter 11
Operational Amplifiers and Applications
Chapter Goals
• Understand the “magic” of negative feedback and the
characteristics of ideal op amps.
• Understand the conditions for non-ideal op amp behavior so
they can be avoided in circuit design.
• Demonstrate circuit analysis techniques for ideal op amps.
• Characterize inverting, non-inverting, summing and
instrumentation amplifiers, voltage follower and first order
filters.
• Learn the factors involved in circuit design using op amps.
• Find the gain characteristics of cascaded amplifiers.
• Special Applications: The inverted ladder DAC and successive
approximation ADC
Differential Amplifier Model: Basic
Represented by:
A = open-circuit voltage gain
vid = (v+-v-) = differential input signal
voltage
Rid = amplifier input resistance
Ro = amplifier output resistance
The signal developed at the amplifier
output is in phase with the voltage applied
at the + input (non-inverting) terminal and
180° out of phase with that applied at the
- input (inverting) terminal.
LM741 Operational Amplifier: Circuit
Architecture
Current Mirrors
Ideal Operational Amplifier
• The “ideal” op amp is a special case of the ideal differential amplifier
with infinite gain, infinite Rid and zero Ro .
v
v  o
id A
and
lim vid  0
A 
– If A is infinite, vid is zero for any finite output voltage.
– Infinite input resistance Rid forces input currents i+ and i- to be zero.
• The ideal op amp operates with the following assumptions:
– It has infinite common-mode rejection, power supply rejection, openloop bandwidth, output voltage range, output current capability and
slew rate
– It also has zero output resistance, input-bias currents, input-offset
current, and input-offset voltage.
The Inverting Amplifier: Configuration
• The positive input is grounded.
• A “feedback network” composed of resistors R1 and R2 is connected
between the inverting input, signal source and amplifier output node,
respectively.
Inverting Amplifier:Voltage Gain
• The negative voltage gain
implies that there is a 1800 phase
shift between both dc and
sinusoidal input and output
signals.
• The gain magnitude can be
greater than 1 if R2 > R1
• The gain magnitude can be less
than 1 if R1 > R2
vs  isR  i R  vo  0
• The inverting input of the op
1 2 2
amp is at ground potential
But is= i2 and v- = 0 (since vid= v+ - v-= 0) (although it is not connected
directly to ground) and is said to
R
vs
vo
is 
 2
and Av 
be at virtual ground.
R
vs
R
1
1
Inverting Amplifier: Input and Output
Resistances
Rout is found by applying a test current
(or voltage) source to the amplifier
output and determining the voltage (or
current) after turning off all
independent sources. Hence, vs = 0
vx  i R  i R
2 2 11
But i1=i2
vx  i ( R  R )
1 2 1
v
R  s  R since v  0
in i
1
s

Since v- = 0, i1=0. Therefore vx = 0
irrespective of the value of ix .
Rout  0
Inverting Amplifier: Example
•
•
•
•

Problem: Design an inverting amplifier
Given Data: Av= 20 dB, Rin = 20kW,
Assumptions: Ideal op amp
Analysis: Input resistance is controlled by R1 and voltage gain is set
by R2 / R1.
AvdB 20log Av , Av 1040dB/20dB 100 and Av = -100
10
A minus sign is added since the amplifier is inverting.
R  R  20kW
1 in
R
Av  2  R 100R  2MW
2
1
R
1

The Non-inverting Amplifier: Configuration
• The input signal is applied to the non-inverting input terminal.
• A portion of the output signal is fed back to the negative input
terminal.
• Analysis is done by relating the voltage at v1 to input voltage vs and
output voltage vo .
Non-inverting Amplifier: Voltage Gain,
Input Resistance and Output Resistance
Since i-=0
R
1
v  vo
1
R R
1 2
and
vs  v  v
id 1
vs  v
1
R R
vo  vs 1 2
R
1
R
v o R1  R2
 Av 

 1 2
R
vs
R
1
1
vs
R  
Since i+=0
in i

Rout is found by applying a test current source to the amplifier output
after setting vs = 0. It is identical to the output resistance of the inverting
amplifier i.e. Rout = 0.
But vid =0
Non-inverting Amplifier: Example
• Problem: Determine the output voltage and current for the given noninverting amplifier.
• Given Data: R1= 3kW, R2 = 43kW, vs= +0.1 V
• Assumptions: Ideal op amp
• Analysis:
R
43kW
Av 1 2 1
15.3
R
3kW
1
vo  Avvs (15.3)(0.1V)1.53V
Since i-=0,

vo
1.53V
io 

 33.3A
R  R 43kW  3kW
2 1
Finite Open-loop Gain and Gain Error
vo  Av  A(vs  v )  A(vs  vo )
1
id
vo
A
Av 

v s 1  A
A is called loop gain.
R
1 v  v
v 
o
1 R R o
1 2
R
1
is called the

R R
feedback factor.
1 2

For A >>1,
R
1
Av  1 2

R
1
This is the “ideal” voltage gain of
the amplifier. If A is not >>1,
there will be “Gain Error”.
Gain Error
• Gain Error is given by
GE = (ideal gain) - (actual gain)
For the non-inverting amplifier,
GE 
1
A
1

 1 A  (1 A )

• Gain error is also expressed as a fractional or percentage
error.
1
A

1
1
FGE   1 A 

1
1 A A

PGE 

1
100%
A
Gain Error: Example
• Problem: Find ideal and actual gain and gain error in percent
• Given data: Closed-loop gain of 100,000, open-loop gain of
1,000,000.
• Approach: The amplifier is designed to give ideal gain and deviations
from the ideal case have to be determined. Hence,
 1
.
10 5
Note: R1 and R2 aren’t designed to compensate for the finite open-loop
gain of the amplifier.

6
A
10
Av 

 9.09x104
• Analysis:
1 A
106
1
105
105 9.09x10 4
PGE
100% 9.09%
5
10

Output Voltage and Current Limits
Practical op amps have limited
output voltage and current ranges.
Voltage: Usually limited to a few
volts less than power supply span.
Current: Limited by additional
circuits (to limit power dissipation
or protect against accidental short
circuits).
The current limit is frequently
specified in terms of the minimum
load resistance that the amplifier
can drive with a given output
voltage swing. Eg: i  5V 10mA
o 500W
v
vo
v
io  i  i  o 
 o
L F R
R R R
L
2 1
EQ
R
 R (R  R )
EQ L 1 2
For the inverting amplifier,
R R R
EQ L 2
Example PSpice Simulations of
Non-inverting Amplifier Circuits
The Unity-gain Amplifier or “Buffer”
• This is a special case of the non-inverting amplifier, which is also
called a voltage follower, with infinite R1 and zero R2. Hence Av = 1.
• It provides an excellent impedance-level transformation while
maintaining the signal voltage level.
• The “ideal” buffer does not require any input current and can drive any
desired load resistance without loss of signal voltage.
• Such a buffer is used in many sensor and data acquisition system
applications.
The Summing Amplifier

Since the negative amplifier
input is at virtual ground,
v
v
1
i 
i  2 i   vo
1 R
2 R
R
1
2 3
3
Since i-=0, i3= i1 + i2,
R
R
vo  3 v  3 v
R 1 R 2
1
2
• Scale factors for the 2 inputs
can be independently adjusted
by the proper choice of R2 and
R1 .
• Any number of inputs can be
connected to a summing
junction through extra
resistors.
• This circuit can be used as a
simple digital-to-analog
converter. This will be
illustrated in more detail, later.
The Difference Amplifier
R
Since v-= v+ vo   2 (v  v )
R 1 2
1
For R2= R1 vo  (v1  v2)
• This circuit is also called a
differential amplifier, since it
amplifies the difference between
the input signals.
v o  v-  i R  v-  i R
• Rin2 is series combination of R1
2 2
1 2
and R2 because i+ is zero.


R R 
R
R

2 v-  2 v • For v2=0, Rin1= R1, as the circuit
 v-  2 ( v  v- )   1

R 1
R 
R 1
reduces to an inverting amplifier.

1
1 
1

• For general case, i1 is a function
R
of both v1 and v2.
2 v
Also, v 
 R R 2
1 2
Difference Amplifier: Example
•
•
•
•
Problem: Determine vo
Given Data: R1= 10kW, R2 =100kW, v1=5 V, v2=3 V
Assumptions: Ideal op amp. Hence, v-= v+ and i-= i+= 0.
Analysis: Using dc values,
R
100kW
A  2 
10
dm
R
10kW
1


Vo  A V V 10(5 3)
dm 1 2 
Vo 20.0 V
Here Adm is called the“differential mode voltage gain” of the difference amplifier.
Finite Common-Mode Rejection Ratio
(CMRR)
A(or Adm) = differential-mode gain
Acm = common-mode gain
vid = differential-mode input voltage
vic = common-mode input voltage
v
v
v  v  id
v  v  id
1 ic 2
2 ic 2
A real amplifier responds to signal
common to both inputs, called the
common-mode input voltage (vic).
In general,
v  v 
vo  A (v  v ) Acm 1 2 
dm 1 2

2 

vo  A (v ) Acm(v )
ic
dm id
An ideal amplifier has Acm = 0, but for a
real amplifier,




Acm v 
v


ic  A v  ic 
vo  A v 

dm id
dm id CMRR 
A


dm 
A
CMRR  dm
Acm
and CMRR(dB) 20log (CMRR)
10
Finite Common-Mode Rejection Ratio:
Example
• Problem: Find output voltage error introduced by finite CMRR.
• Given Data: Adm= 2500, CMRR = 80 dB, v1 = 5.001 V, v2 = 4.999 V
• Assumptions: Op amp is ideal, except for CMRR. Here, a CMRR in dB
of 80 dB corresponds to a CMRR of 104.
• Analysis: v  5.001V 4.999V
id
v  5.001V 4.999V  5.000V
ic
2




v
5.000


ic

V 6.25V
vo  A v 
 25000.002

dm id CMRR 

104 
In the "ideal" case, vo  A v  5.00 V
dm id
6.255.00
% output error
100% 25%

5.00
The output error introduced by finite CMRR is 25% of the expected ideal
output.

uA741 CMRR Test: Differential Gain
Differential Gain Adm = 5 V/5 mV = 1000
uA741 CMRR Test: Common Mode Gain
Common Mode Gain Acm = 160 mV/5 V = .032
CMRR Calculation for uA741
Adm 1000
CMRR 

 3.125x10 4
Acm .032
CMRR(dB)  20log 10 CMRR   89.9 dB

Instrumentation Amplifier
R
vo   4 (va  v )
b
R
3
va  iR  i(2R )  iR  v
2
1
2 b
v v
i 1 2
2R
1
R  R 
vo   4 1 2 (v  v )
R  R  1 2
3
1
NOTE
Combines 2 non-inverting amplifiers
with the difference amplifier to
provide higher gain and higher input
resistance.
Ideal input resistance is infinite
because input current to both op
amps is zero. The CMRR is
determined only by Op Amp 3.
Instrumentation Amplifier: Example
• Problem: Determine Vo
• Given Data: R1 = 15 kW, R2 = 150 kW, R3 = 15 kW,R4 = 30 kW V1 = 2.5 V,
V2 = 2.25 V
• Assumptions: Ideal op amp. Hence, v-= v+ and i-= i+= 0.
• Analysis: Using dc values,
R







R  30kW  150kW 
4
1
 22
A 
1 2  


dm R
R  15kW  15kW 
3
1 
Vo  A (V V ) 22(2.5 2.25) 5.50V
dm 1 2

The Active Low-pass Filter
Use a phasor approach to gain analysis of
this inverting amplifier. Let s = jw.
v˜o ( jw) Z2( jw )
Z jw  R
Av 

1
1
v˜( jw)
Z ( jw )
1
1

R
R
2 jwC

2
Z ( jw)

2
1
jwCR 1
R 
2
2 jwC
R
R e j
1
Av  2
 2

R (1 jwCR ) R (1 jw )
1
2
1
wc
wc  2f c  1  f c  1
RC
2R C
2
2

fc is called the high frequency “cutoff” of
the low-pass filter.

Active Low-pass Filter (continued)









j









• At frequencies below fc (fH in the
figure), the amplifier is an
inverting amplifier with gain set
by the ratio of resistors R2 and
R1 .
• At frequencies above fc, the
amplifier response “rolls off” at
-20dB/decade.
• Notice that cutoff frequency and
gain can be independently set.








j








1(w /w )]
R
R
R
j[

tan
e
e
2
2
c
Av  2


e
1(w /w )
R (1 jw )

2

2
jtan
1
c
 w 
 w 
wc
phase
R 12    e
R 1   magnitude




1
1
w 
w 
 c 
 c 
Active Low-pass Filter: Example
• Problem: Design an active low-pass filter
• Given Data: Av= 40 dB, Rin= 5 kW, fH = 2 kHz
• Assumptions: Ideal op amp, specified gain represents the desired lowfrequency gain.
• Analysis: A 1040dB/ 20dB 100
v
Input resistance is controlled by R1 and voltage gain is set by R2 / R1.
The cutoff frequency is then set by C. R
R  R  5kW
Av  2  R 100R  500kW
and
1 in
2
1
R
1
1
1
C

159pF
2f R 2 (2kHz)(500kW)
H 2 
The closest standard capacitor value of 160 pF lowers cutoff frequency
to 1.99 kHz.

Low-pass Filter Example PSpice Simulation
Output Voltage Amplitude in dB
Output Voltage Amplitude in Volts (V) and Phase in Degrees (d)
Cascaded Amplifiers
• Connecting several amplifiers in cascade (output of one stage connected to
the input of the next) can meet design specifications not met by a single
amplifier.
• Each amplifer stage is built using an op amp with parameters A, Rid, Ro,
called open loop parameters, that describe the op amp with no external
elements.
• Av, Rin, Rout are closed loop parameters that can be used to describe each
closed-loop op amp stage with its feedback network, as well as the overall
composite (cascaded) amplifier.
Two-port Model for a 3-stage Cascade
Amplifier
• Each amplifier in the 3-stage cascaded amplifier is replaced by its 2-port




model.
R
R





inB


inC
A
vo  A vs
A 

 vC
vA R
 R  vBR
R

 outA
inB   outB inC 
vo
Av 
A A A
SinceRout= 0
vA vB vC
vs
Rin= RinA and Rout= RoutC = 0
A Problem: Voltage Follower Closed
Loop Gain Error due to A and CMRR
The ideal gain for the voltage
follower is unity. The gain error
here is:
A
1
CMRR
GE1 Av 


1


1 A1



2(CMRR)


v v
v  s o
ic
2
v  vs  vo
id
vs  vo 

vo  A vs  vo
2(CMRR)
















1
vo
2(CMRR)
Av  


vs
1


1 A1



2(CMRR)


A 1


Since, both A and CMRR are
normally >>1,
1
1
GE 
A CMRR
Since A ~ 106 and CMRR ~ 104 at
low to moderate frequency, the gain
error is quite small and is, in fact,
usually negligible.
Inverted R-2R Ladder DAC
•
•
•
•
A very common DAC circuit architecture with good precision.
Currents in the ladder and the reference source are independent of digital
input. This contributes to good conversion precision.
Complementary currents are available at the output of inverted ladder.
The “bit switches” need to have very low on-resistance to minimize
conversion errors.
Successive Approximation ADC
• Binary search is used by the SAL to determine vX.
• n-bit conversion needs n clock periods. Speed is
limited by the time taken by the DAC output to
settle within a fraction of an LSB of VFS , and by the
comparator to respond to input signals differing by
small amounts.
• Slowly varying input signals, not changing by
more than 0.5 LSB (VFS /2n+1 ) during the
conversion time (TT = nTC) are acceptable.
• For a sinusoidal input signal with p-p amplitude =
fc
VFS, f 
o 2n2(n1)
• To avoid this frequency limitation, a high speed

sample-and-hold circuit is used ahead of the
successive approximation ADC.
• This is a very popular ADC with fast conversion
times, used in 8- to 16- bit converters.
SAADC: Block Diagram
SAADC: Method of Operation