Transcript Critical remarks on two CARIOCA chips

Presented by A.Kashchuk
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
LHCb muon front-end chip
by user’s eyes
Why 2 chips?
CARIOCA negative
CARIOCA positive
1.What I like and accept
2.What I don’t like and can not accept
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
It is possible: “Bipolar”
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
It was clear already in Dec.1999,
that we’ll not find perfect chip...
In order to satisfy specific requirements
of the LHCb experiment,
it has been suggested in January 2000
(to Burkhard and Pierre)
to start designing own LHCb Muon
ASIC for MWPC
using submicron CMOS
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
Innovation in the CMOS amplifier
is the active feedback (see P.Jarron et al.,1995)
It provides in CMOS
fast shaping and
low noise at high Cdet
Input
Output
SPICE model of the Current Amplifier based on the active feedback
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
I like that
 LHCb Muon front-end chip is designed in 0.25 micron CMOS
technology of IBM;
 It based on the new active feedback schematics which provides
in CMOS fast shaping and low noise at high Cdet;
 It is radiation hard;
 It has single power supply +2.5V and low power consumption;
 It can also be applied for RPC;
 It can be optimized for negative and positive input polarities
I like also that
 Its further integration with DIALOG chip can provide compact
and cost-effective solution for any number of channels/board
needed in various regions of the LHCb Muon System
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
Input polarity definition in CARIOCA chip versions:
Input current must be added to bias current
to maximize dynamic range
Positive version
nMOS
If=Iin+Ibias
22-23.04.2002
Muon meeting, CERN
Negative version
pMOS
-If=Iin+Ibias
A.Kashchuk
What do not like
I’ll show problems (and my statements)
I suggest changes in schematics of the
CARIOCA preamplifiers
 Stability margin is not enough;
 Optimization of CMOS transistor parameters within
feedback loop has to be done;
 Cfeed should be avoided
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
Equivalent circuit and its impulse response:
CARIOCA negative
Qin =1fC
Parameters taken from chip:
G5=42.35mA/V, G6=1.1mA/V, G7=52.6uA/V, Cfeed=400fF, capacitors
Model is ringing
even at small Cdet
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
CARIOCA negative (cont.)
Cdet is increased
G5=42.35mA/V, G6=1.1mA/V, G7=52.6uA/V, Cfeed=400fF, capacitors
Model
is unstable
at Cdet=10-100pF
Note:
similar response
has been reproduced
on real schematics
with increasing G7
Being connected to SPB,
all 16 channels
of CARIOCA negative
generate 80 MHz
at any threshold
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
Equivalent circuit and its impulse response:
CARIOCA positive
Parameters taken from chip:
G5=42.35mA/V, G6=1.4mA/V, G7=19uA/V, Cfeed=400fF, capacitors
Model is close
to instability
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
Both versions will be stable at reduced G7 (factor10)
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
As shown,
without Cfeed it is unstable again
Cfeed=0.4pF introduces
dynamic capacitor
of about 120 pF
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
It’ll be stable without Cfeed at reduced G6 (factor 10)
Only G5 is taken from chip
Excellent
response
Excellentimpulse
response
Excelent
response
Cdet=0-1000pF,
50% amplitude reduction
at Cdet=1000pF
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
Note: feedback loop in CARIOCA
has been designed incorrectly
in both preamplifiers
As a result:
CARIOCA negative can not be used;
CARIOCA positive has small stability margin
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
I suggest changes in schematics
Preamplifiers (cont.)
 Current-mirrors from preamplifiers to the shaper stage
(providing about 3mV/fC gain) must be avoided;
 Existing gain (25mV/fC) has to be used;
 Proposed schematics will also reduce voltage spread propagated to the
next stages
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
Existing voltage gain has to be used,
it will also reduce voltage spread
propagated to the next stages
Negative version
Vout to shaper
22-23.04.2002
Muon meeting, CERN
Positive version
Vout to shaper
A.Kashchuk
 One ASIC versus two
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
Solution 1: by increasing Ibias
How I have modified positive version to work with negative signals:
To the existing connections
within CARIOCA chip
Iin (dummy input)
Increased
Ibias=60uA instead of 6uA
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
MWPC on cosmics
equipped by the positive board
with the negative input signal
Gas 40Ar/50CO2/10CF4, Th=+/-200mV
Sigma 2.9ns
within requirements
TDC spectrum at 3.15kV
(OR of 3 wire strips 6mm width x 25cm length each one)
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
Solution 2: by switching Ibias polarity
Both main and dummy inputs
will be used in this version
to save threshold polarity
22-23.04.2002
Muon meeting, CERN
Only one bias current is ON
A.Kashchuk
I suggest changes in schematics
Shaper
 Time constants cancelled in CARIOCA: 9 and 80ns
I did not see how looks difference of the real signal and its approximation
by sum of the exponents implemented in CARIOCA;
 I’ll show (see below), that another time constants have to be cancelled,
using another optimization criterion
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
Pulse width vs HV measured with 241Am-source
shows
HV=3.15kV
Average pulse width shows tail
Bursts of pulses occur
when tail crosses threshold
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
ASDQ++ has no such ‘defect’ up to 3.3kV
Wire and Cathode readout
(average pulse FWHM and 10% width vs HV, 241Am,
gas 40Ar/50CO2/10CF4)
Pulse width (ns)
Rise starts at 2.9-2.95kV!
Carioca_v0
ASDQ++
pn#2c#10
10%width
200
p#3c#10
150
10%width
Carioca+
ASDQ++
max
100
50
0
2.6
2.7
2.8
2.9
3
3.1
3.2
HV (kV)
22-23.04.2002
Carioca+/-
Muon meeting, CERN
A.Kashchuk
3.3
3.4
Base Line Restorer
(BLR must reduce base line fluctuations introduced by another sources)
 Spread of DC levels produced by BLR
on discriminator inputs must be avoided;
(See Werner’s report)
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
Discriminator
 Differential thresholds should be changed to single polarity;
 Threshold has to be common for even and odd channels;
 Hysteresis has to be studied better (can be reduced on board)
22-23.04.2002
Muon meeting, CERN
A.Kashchuk
Conclusion
 Very good general architecture of CARIOCA chip (dummy channel
followed differential stages) has been implemented rather bad
 ‘Bipolar’ solution ‘One ASIC instead of two’ is real one.
We have to work effectively to implement many improvements
for submission in July 2002
22-23.04.2002
Muon meeting, CERN
A.Kashchuk