Transcript Architecture-Level Power Modeling

Architecture-Level
Power Modeling
N. Kim, T. Austin, T. Mudge, and D. Grunwald.
“Challenges for Architectural Level Power Modeling.”
In Power Aware Computing, (R. Melhem and R. Graybill eds.), Kluwer, 2001.
Kevin Skadron
Mircea Stan
U.Va.
Department of Computer Science
Slide 1
LAVA
Who Cares?

Power is now a first-level design constraint for both
embedded/mobile and high-performance/general-purpose
processors

Battery life (eg, laptops)

Heat removal and package cost

Degradation and lifetime
Architects don’t have good tools to model this
U.Va.
Department of Computer Science
Slide 2
LAVA
Modeling

What architects normally do: model behavior/performance
at the cycle level (eg, SimpleScalar)
 Many
abstractions and simplifications
– Examples: I-cache, memory buses
 Faster
than a more detailed model; still good enough

Power and heat, however, require more implementation
detail

Current power-performance simulators try to omit the extra
detail by using abstractions or analytic models
U.Va.
Department of Computer Science
Slide 3
LAVA
Current Arch.-Level Power Simulators

Wattch (Brooks et al.)
 Doesn’t
model anything outside the core (eg, external bus)
 CACTI-based models for large structures (cache, branch predictor,
register file, instruction window, etc.)
– Tuned using Intel data

SimplePower (Vijaykrishnan et al.)
 Adds
bus and memory modeling, also I/O pads
 Look-up-tables (LUTs)

Tempest (Cai & Lim)
 Power
density
 Chip-level thermal modeling

No one: data sensitivity, clock tree, global interconnect
U.Va.
Department of Computer Science
Slide 4
LAVA
Typical Power-Performance Modeling
Technology
parameters
Cycleaccurate
performance
model
U.Va.
Micro-arch.
config
activity
factors
Department of Computer Science
Slide 5
Static
power model
Dynamic
power
estimation
cycle-by-cycle
statistics
LAVA
Power Basics
P = ½ACV2f + AVIshort + VIleak

A = activity factor

C = capacitance

V = dynamic voltage

f = frequency
 Ishort
= short-circuit current during switching
 Ileak
= leakage current
U.Va.
Department of Computer Science
Slide 6
LAVA
Power Basics
P = ½ACV2f + AVIshort + VIleak
P = ACVDDVswingf + AVIshort + VIleak

A = activity factor

C = capacitance

V = dynamic voltage

f = frequency
 Ishort
= short-circuit current during switching

= duration of short-circuit current
 Ileak = leakage current


Why averages don’t work:
Bursty behavior, dI/dt, peak current, temperature
U.Va.
Department of Computer Science
Slide 7
LAVA
Better Simulation Method
P = ACVDDVswingf + AVIshort + Vileak
sum over all blocks
U.Va.
Department of Computer Science
Slide 8
LAVA
Typical Power-Performance Modeling
Technology
parameters
Cycleaccurate
performance
model
U.Va.
Micro-arch.
config
activity
factors
Department of Computer Science
Slide 9
Static
power model
Dynamic
power
estimation
cycle-by-cycle
statistics
LAVA
Metrics

What metrics do we care about?
 Execution
time
 Energy (battery life)
 Energy-delay product
 Energy-delay2 product?
 Power density (temperature)
 Temperature
 DI/dt
 Peak power dissipation

Might also care about these at finer granularities:
micro-arch. blocks, decoders, circuits, etc.
U.Va.
Department of Computer Science
Slide 10
[sec or IPC]
[W]
[Ws]
[Ws2]
[W / mm2]
[K or °C]
LAVA
Basic Techniques for Power Efficiency

Leakage: turn things off (but you lose the data)
 Resize
structures
 Turn off idle structures
 Turn off entries, eg cache decay
 4T RAM cells?

Dynamic: reduce activity factors
 Clock
gating
 Resize structures
 “Utility” predictor
 Throttle processor width (eg, fetch width)
 Filter caches
 Datapath resizing
P = ½ACV2f + AVIshort + VIleak
 etc.
U.Va.
Department of Computer Science
Slide 11
LAVA
Simulating Power for Greater Accuracy
P = ½ACV2f + AVIshort + VIleak
In all these cases, we want to find relevant power-related
parameters (esp. effective switching capacitance C)
-- performance model provides A

More detailed block-specific power information
(circuit design style, etc.)

Switching activity (Hamming distance)

Interconnect (floorplanning, approx. area)

Clock tree (H-tree vs. balanced H-tree)

Random logic (empirical models)

Busses, transactions, durations (pull-up/pull-down/hi-Z, read
vs. write, etc.)
U.Va.
Department of Computer Science
Slide 12
LAVA
Simulation Challenges

Need leakage models - f(T)

Need temperature models

Eventually want to integrate all these into a fast simulator
 This
is a research challenge in its own right
U.Va.
Department of Computer Science
Slide 13
LAVA