Transcript NIKHEF_HD-FE-Proposal

Outer Tracker Front-End Layout
Distribution of Signals and Bias
NIKHEF/Heidelberg
October 2002
1
Assumptions about OTR Configuration
• Three identical tracking stations (ST1, ST2, ST3) of four planes
(XVVX) of straw tube modules.
• For the distribution of TFC, I2C, and bias, tentatively we propose to
subdivide each station in four quadrants.
• Each quadrant needs services for four planes, each one consisting of
eight 340mm-wide (2 x 64 wires) straw modules and one 170mm-wide
(2 x 32 wires) straw module. The distribution of services is the task of
the Tracker Quadrant Distribution Box (TQ Distribox).
• The TQ Distribox fulfills the following functions:
– Distributes the timing and trigger signals (TFC)
– Receives and distributes the slow control signals (ECS)
– Act as patch panel for the power (High Voltage and Low Voltage)
2
Why 4 Quadrants?
• Mechanical constraints:
– Must be able to open station in two halves independantly without disconnecting
cables  distribution boxes must be solidal to half station.
• Timing constraints:
– Module to module clock-phase differences < 1 ns  limit max cable length (half
station length ~ 3 M = 15 ns).
• Electrical constraints:
– Minimize ground loops, mount distribution box on detector frame.
3
Detector Layout
TFC
ECS
Power (HV,LV)
TQ-distribox
TQ-distribox
TFC
ECS
Power (HV,LV)
Fibers to L1 Buffer
Fibers to L1 Buffer
Tracker
Quadrant
Fibers to L1 Buffer
TFC
ECS
Power (HV,LV)
Fibers to L1 Buffer
TQ-distribox
TQ-distribox
TFC
ECS
Power (HV,LV)
4
Module Front-End
•
The details of control and power distribution depend on the implementation of
the FE electronics and the interconnection between FE boards.
–
•
TFC :
–
–
–
–
–
•
The main parts of the Module FE are: ASDBLR chips, OTIS TDCs, GOL and ADC.





OTIS, GOL
OTIS
OTIS,GOL
OTIS
ASDBLR


OTIS, GOL (ADC, TTCrx may be in TQ Distribox)
ADC, may be in TQ Distribox)
-3 V
+3 V
+2.5 V



ASDBLR
ASDBLR, (ADC)
OTIS, GOL, (ADC)
HV

HV boards
Clock
BC Reset
L0 Reset
L0 Trigger
Test Pulse
ECS:
•
•
•
LV:
–
–
–
•
I2C
(JTAG
HV:
–
5
Signals To Distribute
Fiber to TFC
Fiber to ECS
Cables to HV supply
TQ-distribox
Clock, trigger and resets (36x)
•
4 wires: +5V, Return, -5V, Return
I2C: 4 planes x 1 or 2 daisy chain/plane
–
•
The OTIS has one fast reset, the TFC signals are: Bunch Clock, L0 Trigger, Reset and Testpulse.
To distribute these signals CAT5 cable can be used (max. 4 differential signals). If in a later
version of the OTIS a separate Bunch Count Reset and L0 Reset are used, the resets could be
coded, because it is preferred to use CAT5 cable instead of flatcable to distribute the TFC
signals.
LV: 4 planes x 9 FE-boxes/planes  36 LV cables
–
•
Power
low voltage (36x)
TFC: 4 planes x 9 FE-boxes  36 CAT5 cables
–
•
I2Cbus (8x)
Power
high voltage (36x)
Cables to LV supply
dependant on ADC type
Monitor signals: 4 planes x 9 FE-boxes  36 cables
–
Temperature, +3V, -3V, 2.5V
6
TQ Distribution Box
TTC fiber
+5 V
SPECS fiber
36 channel HV
-5 V
Addr
temp
addr
TTCrx
I2C
ADC
filter
JTAG
L0Accept
BrcstStr
Clock40Des1
Brcst<7:0>
Specs Slave
?
clk
JTAG
rst
PLL
scope
outputs
3.3V
reg
2.5V
reg
3.3
2.5
I2C
Decoder
Clock
Testpulse
Reset
Bcreset
JTAG
High Voltage Patchpanel
ADCs
Mux
LVDS Drivers
(ALCAPONE)
4 outputs
36 outputs
(4 x 9)
TFC
TFC
I2C
I2C
36 inputs
(4 x 9)
Monitor
signals
-5V
+5V
Monitor
signals
LV
36 outputs
(4 x 9)
36 outputs
(4 x 9)
-5V
+5V
LV
HV
HV
7
Module FE-box Layout
• Contains:
–
–
–
–
16 ASDBLR
4 OTIS
1 GOL
(1 ADC)
• One board per plane :
– obvious!
• One style board:
– Not enough space between planes of a station
– We have anyway a number of half-modules
• Chip waste:
– Not more than 1 OTIS per board
– OTIS and ASDBLR separated
– Not more then 2 ASDBLR per board
8
Proposal For ASDBLR / OTIS Board(s)
tpls clk/trig/rst data
8
4
term
term
I2C addr
2
power
4
3.3 2.5 +3 -3
filter
min.
42 pins
connector
OTIS
32
+3 -3
+3 -3
tpls data ref power
tpls data ref power
tpls data ref power
tpls data ref power
testpulse
16
-3
+3
8
8
ref
-3
+3
8
ref
8
16
8
ref
ASDBLR ASDBLR
8
testpulse
min.
38 pins
connector
ref
ASDBLR ASDBLR
8
8
9
Signal and Voltage Distribution Scenarios
Separate GOL and AUX boards
Integrated GOL and AUX boards
10
How Could an Integrated AUX/GOL Board Look Like?
Data
TFC
I2C Addr I2C
8 pin RJ45
connector
4
Reset
decoder
+5V
4 pins Rj11
connector
2.5V
reg
out
Clk
term
GOL
I2C
Monitor
signals
LV
-5V
+3V
reg
-3V
reg
+3
-3
8 pin RJ45
connector
2.5
filter
PU-reset
in
Temp
term
32
2.5 +3 -3
4
2
power addr I2C
8
4
data clk/trig/rst tpls
4
8
tpls clk/trig/rst data
2
4
I2C addr
2.5 +3 -3
power
2.5 +3 -3
4
2
power addr I2C
8
4
data clk/trig/rst tpls
4
8
tpls clk/trig/rst data
2
4
I2C addr
2.5 +3 -3
power
Remember that in the task division:
• AUX Board assigned to NIKHEF (considered as part of FE)
• GOL Board assigned to HD/Dresden (considered as part of L1)
An integrated AUX/GOL board is possible without conflict
• task division will not be altered
• HD will design the GOL part, while NIKHEF the rest
• NIKHEF will integrate the two designs in the final layout
• NIKHEF will provide enough geometry/connectors specs to HD such
that HD design will resemble final layout as closely as possible
11
Front-End Layout On “Wide” Detector Module
GOL
OTIS
ASDBLR
OTIS
ASDBLR
ASDBLR
ASDBLR
HV board
12
Front-End Layout On “Narrow” Detector Module
GOL
OTIS
ASDBLR
ASDBLR
HV board
13
Nota Bene
• The GOL/ADC board is about 120 mm wide, together with gas, high
voltage and mechanical support it must fit in the 170 mm module.
• The OTIS board are in two types (left and right), according to where
the GOL connector is, in order to avoid the use of cable in the module.
• The OTIS and ASDBLR chips are in one plane, so they can be cooled
by the case of the module-box. Special care must be taken to ensure
the cooling of the LV-regulators portion of the GOL/ADC board.
• As no cable is used to connect the OTIS data to the GOL the signals
can be LVTTL, but LVDS is preferred (LVDS receivers needed for
the GOL).
• LVDS repeaters needed to distribute TFC signals.
• I2C signals can be distributed using standard telephone cable and
connectors (RJ11). We propose to have separate I2C bus lines for the
control of the chips and for parameter monitoring.
14
Signal And Power Connections From TQ Distribox to FE
Fiber to ECS Cables to HV supply
Fiber to TFC
Cables to LV supply
TQ-distribox
Clock, trigger and resets (36x)
Power
low voltage (36x)
Power
high voltage (36x)
I2Cbus (8x)
Matched Cables
Fibers to
L1 Buffer
Data
HV
LV
I2C
Gas
TFC
Data
HV
LV
I2C
Gas
TFC
LV
HV
LV
I2C
Gas
TFC
HV
Data
I2C
Gas
Gas
Gas
I2C
TFC
HV
LV
LV
Gas
TFC
Data
LV
HV
I2C
Gas
Gas
LV
Data
Gas
Gas
Data
TFC
Gas
HV
Data
I2C
Gas
Gas
TFC
Data
LV
HV
Gas
Data
HV
LV
Gas
I2C
TFC
Gas
Data
HV
LV
Gas
Gas
I2C
TFC
Data
HV
LV
Gas
Gas
Top view of a part of the Tracker Quadrant
15
Details of TFC Distribution
• TTCrx decoding in TQ Distribox
– See LHCb 2001-017 TFC Broadcast Format
• Reset decoding in Front-end Module
– Needed to enable the distribution of 5 TFC signals via CAT5 cable
• Distribution of TFC signals
– Do we need LVDS repeaters in the Front-end Module?
16
TTCrx Decoding
Clock
Test-Pulse
Brcst(7:2)
0001xx
L0-Reset
01xx01
BC-Reset
Brcst(0)
Test-Pulse
Reset
17
Reset Decoding
Clock
Reset
BC-Reset
L0-Reset
•
Both decoding schemes in one Actel antifuse FPGA
18
Distribution of TFC signals without LVDS repeaters
Power Supply
GOL board
VCC
VCC
100
Distribox
LVDS
driver
GOL
4 meter
15 cm stubs
Jitter ~ 70 ps
Max phase difference between OTIS < 400 ps
OTIS
OTIS
OTIS
OTIS
4 OTIS boards
19
Distribution of TFC signals with LVDS repeaters
Power Supply
Distribox
GOL board
VCC
VCC
LVDS repeater
LVDS
driver
4 meter
GOL
Jitter ~ 50 ps
Phase difference between OTIS < 200 ps
OTIS
OTIS
OTIS
OTIS
4 OTIS boards
20
Conclusions on TFC Signal Distribution
 TFC Signals can be distributed without the use of an LVDS repeater in the
Front-end box
 No significant increase of the jitter (50 ps > 70 ps)
 Less components needed: cheaper, less dissipation
 No extra propagation delay
 Phase difference between OTIS chips is a bit higher <400 ps compared to < 200 ps
 Higher demands on board layout
21