Transcript A Fast, Analytical Estimator for the SEU

A Fast, Analytical Estimator for the
SEU-induced Pulse Width in
Combinational Designs
By:
Rajesh Garg
Charu Nagpal
Sunil P. Khatri
Department of Electrical and Computer Engineering,
Texas A&M University, College Station, TX
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Outline
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Introduction
Previous Work
Objective
Approach
Classification of Radiation Particle Strikes
 Our Model
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Experimental Results
Conclusions
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Introduction
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Modern VLSI Designs
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Single Event Upsets (SEUs) or Soft Errors
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Troublesome for both memories and combinational logic
Becoming increasingly problematic even for terrestrial
designs
Applications demand reliable systems
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Vulnerable to noise effects- crosstalk, SEU, etc
Need to efficiently design radiation tolerant circuits
Analyze circuits early in design flow
Hence need SEU robustness metric
Harden the circuits using these metrics
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Approach depends on level of protection required
Need to satisfy delay, area and power constraints
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SEU Robustness Metrics
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SPICE based simulation of SEU events
Most accurate metric possible
 Computationally expensive
 Too many scenarios required to be simulated
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Amount of charge dumped
 State of circuit inputs
 Need to simulate all nodes in a circuit
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Hence we need an efficient and accurate SEU
robustness metric
This is the focus of this talk
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SEU Robustness Metrics
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Accurate and efficient models for SEU events
Can be used to harden a circuit
 Requires solving of non-linear differential equations.
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Our metric is based on the pulse width of voltage
glitch due to a radiation strike
Good measure of SEU robustness
 Based on the pulse width, we can upsize susceptible
gates
 Easily incorporated in design flow
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Radiation Particle Strike
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Effects of radiation particle strike
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Neutron, proton and heavy cosmic ions
Ions strike diffusion regions
Deposit charge
Results in a voltage spike
Radiation particle strike is modeled by a current pulse as
where: Q is the amount of charge deposited
ta is the collection time constant
tb is the ion track establishment constant
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Previous Work
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Device-level simulation: Dodd et. al 1994, etc
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Logic-level simulation: Cha et. al 1996
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Accurate but very time consuming
Not practical for circuit hardening
Abstract transient faults by logic-level models
Gate-level timing simulators are used
Highly inaccurate as a robustness metric for hardening
purposes
Circuit-level simulation:
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Intermediate between device and logic level simulation
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Previous Work
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Shih et. al 1992 solve transistor non-linear differential equation
using infinite power series
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Dahlgren et. al 1995 presented switch level simulator
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Computationally expensive
Electrical simulations are performed to obtain the pulse width of a voltage
glitch, using the R and C values of a gate
Pulse width for other R and C values are obtained using linear relationship
between the obtained pulse width and the new R and C values
Cannot be used for different values of Q
Mohanram 2005 reports a closed form model for SEU induced
transient simulation for combinational circuits
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Linear RC gate model is used
Ignores the contribution of tb in iseu(t) – we find that this results in 10%
error
Results in lower accuracy
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Objective
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Develop an analytical model for SEU induced transients
in combinational circuits
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Closed form analytical expression for the pulse width of
voltage glitch
Accurate and efficient
Applicable to
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Any logic gate
Different gate sizes
Different gate loading
Incorporates the contribution of tb time constant
Can be easily integrated in a design flow
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Our Approach
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Radiation particle strike at the output of INV1
Implemented using 65nm PTM with VDD=1V
Radiation strike: Q=150fC, ta=150ps & tb=50ps
M1ininSaturation
Saturation
M1
Models Radiation
M1
M2in
inSaturation
Saturation
M1
in
Linear
M2
in
Saturation
Particle Strike
M2
in Drain-Bulk
Cutoff
M1 and M2 operate in different regions
during radiation-induced transients
M2’s
M2
in Cutoff
Our approach estimates the pulsediode
widthisofON
the transient by modeling these regions
INV1 cannot be modeled accurately by a linear RC model (as was done in several
previous approaches)
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Classification of Radiation Strike
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INV1 can operate in 4 different cases depending
upon voltage glitch magnitude VGM (=Va)
Case 1: VGM ≥ VDD + 0.6V
 Case 2: VDD+|VTP| ≤ VGM < VDD + 0.6V
 Case 3: 0.5*VDD ≤VGM <VDD+|VTP|
 Case 4: VGM < 0.5*VDD

Different analytical models are applicable to different
cases to compute pulse width of the voltage glitch
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Model Overview
Given a gate G, its input
state, the gates in the fanout
of G and Q, ta and tb
Cell library data IDS(VDS)
forVGS=1 and 0, CG and CD
Determine the value of VGM &
case of operation
Pulse Width is 0
Yes
If Case==4
No
If Case==1 use
its model to
compute t2
Compute t1
If Case==2 use
its model to
compute t2
Compute Pulse Width as t2-t1
If Case==3 use
its model to
compute t2
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Voltage Glitch Magnitude (VGM)
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IDS of NMOS transistor with gate terminal at VDD
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Differential equation for radiation induced voltage transient at
output of INV1
(1)
Green Known
Va(t)
Red  Unknown
VGM
Again integrate
Integrate
Equation
Equation
1 from1
Now VGM = Va(TVGM)
with initial condition (Vdsat,
(0, 0) to (Vdsat
Va , Tsat)
Tsat) and with
I DS
 K 3  K 4 VDS
Va
with I DS
Obtain
 VDST/VGM
Rnby
differentiating Va(t) and
solving
Solve
for dV
T a(t)/dt = 0
sat
* Details can be found in the paper
Vdsat
Tsat
TVGM
t
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Voltage Glitch Magnitude (VGM)
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VGM = Va(TVGM) where
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X’, Y’ and Z’ are constants defined in the paper
max
is the time when iseu(t) is at its maximum value
Tseu
Diff. eq. for radiation induced voltage transient at output of INV1
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Does not include the drain to source current of M2 (PMOS)
Accurate for Case 3 and 4
In some cases, Case 2 VGM value can be diagnosed as Case 1- Pessimistic
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Next Steps
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Once we know VGM , we know which case is
applicable (among cases 1, 2, and 3).
The magnitude of the SET induced glitch is t2 – t1
Next, we find an expression for t1 (common for all 3
cases)
Then we will find expressions for t2 (separately for each
of the 3 cases)
Note that case 4 is not of interest since the glitch
magnitude is less than VDD/2 in case 4.
Lets do this over the next few slides…
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Expression for t1
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If VGM > 0.5*VDD then
there is a glitch
To obtain t1 , substitute
Va(t1) = 0.5*VDD and solve
for t1 using initial guess t1a
Green Known
Va(t)
Red  Unknown
VGM
0.5*VDD
Vdsat
Tsat
t1
TVGM
t
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Expression for t2 : Case 1
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For Case 1, VGM ≥ VDD+0.6V
Va(t3) = VDD +|VTP|
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IDS of PMOS M2 is zero
iseu (t3) = IDS of M1
Also ignore tb
This gives us t3 below
t3
VDD+|VTP|
Use, Va(t) = VDD +|VTP|
at t = t3 as initial condition
for integration.
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Expression for t2 : Case 1
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Va(t)
Approximate iseu(t) by
a straight line
iseu(t)
Va(t)
Integrate Equation 1 with initial
condition (VDD+|VTP|, t3)
VGM
Red  Unknown
VDD+|VTP|
Substitute Va(t) = 0.5*VDD for
0.5*VDD
t = t2 and solve for t2 by
performing a quadratic
a1
expansion around initial guess t 2
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Green Known
VDD|VTP |
VDD / 2
0.5( I DS
 I DS
)
t1
t3
t2
t* t
P, Q, R and t* are constants defined in the paper
Details of derivation of t2 can be found in the paper
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Expression for t2 : Case 2
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For Case 2:
Va(t)
VDD+|VTP|≤VGM<VDD+0.6V
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Again use initial condition,
Va(t)=VDD+|VTP| at t = t3
Integrate
Equation
1 with initial
To obtain
t2 , substitute
(VDD+|V
|, t3)
Vcondition
(t )=0.5*VDD
andTPsolve
Green Known
VGM
Red  Unknown
VDD+|VTP|
0.5*VDD
a 2
for t2 by using initial guess t 2a 2
t1
TVGM t3
t2
t
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Expression for t2 : Case 3
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For Case 3:
0.5*VDD≤VGM<VDD+|VTP|
To obtain t2 , substitute
Va(t2)=0.5*VDD and solve
for t2 by using initial guess t 2a 2
Green Known
Va(t)
Red  Unknown
VGM
0.5*VDD
Vdsat
Tsat
t1
TVGM
t2
t
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Experimental Results
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Implemented our model in Perl
Library of INV, NAND and NOR gates
Using 65nm PTM model card with VDD=1V
 Characterized each gate for IDS, CG and CD
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Applied our model to INV and NAND2
For different values of Q, ta and tb
 Different gate sizes and loads
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Our model is 1000X faster compared to SPICE
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Experimental Results
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Radiation particle strike at the output INV1 with
Q=150fC, ta=150ps and tb = 50ps
INV1 with input 1
INV1 with input 0
Load
Size
PWS(ps)
PWM(ps)
% Error
PWS(ps)
PWM(ps)
% Error
1
1
533
533
0
517
522
0.97
1
2
414
415
0.24
404
410
1.49
1
4
292
296
1.37
285
298
4.56
1
6
213
223
4.69
208
231
11.06
1
8
142
146
2.82
140
141
0.71
3
1
552
553
0.18
535
533
-0.37
3
2
432
434
0.46
420
420
0
3
4
308
315
2.27
301
306
1.66
3
6
227
239
5.29
221
221
0
3
8
147
152
3.4
147
148
0.68
AVG
2.07
2.15
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Experimental Results
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NAND2 gate with Q=150fC, ta=150ps and tb = 50ps
Average pulse width estimation error compared to SPICE
INPUT 11
INPUT 00
INPUT 01
INPUT 10
Load
Size
% Error
% Error
% Error
% Error
1
1
0
-0.74
-0.19
-0.56
1
2
0.78
1.05
0.24
-0.24
1
4
3.05
0.71
2.41
1.67
1
6
10.34
-
7.55
-0.45
3
1
0.58
0.24
-0.55
-0.36
3
2
1.25
2.39
-0.24
0
3
4
4.01
0.69
1.64
1.27
3
6
3.8
-
0
0
2.97
0.97
1.6
0.57
AVG
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Conclusion
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A SEU robustness metric is required to design radiation tolerant
circuits efficiently
We presented an analytical model to compute this metric (which is
the pulse width of the SEU induced glitch)
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Our model is accurate and efficient
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Pulse width estimation error is 3% compared to SPICE
Our method is 1000X faster than SPICE
Our model gains accuracy
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Pulse width of the glitch is a good measure of SEU robustness
By using the transistor current model (and avoiding a linear RC model for
the gate)
By including the contribution of tb
Our model can be easily incorporated in a design flow to test
robustness. Based on the results, hardening can be performed.
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Thank You
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BACKUP SLIDES
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Voltage Glitch Magnitude (VGM)
 IDS
of NMOS transistor with gate terminal at
VDD
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For 65nm PTM model card Vdsat< 0.5*VDD
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Integrate Eq. 1 from Va(t)=0 at t=0 to Va(t)=Vdsat at t=Tsat
using IDS = Va/RDS
Solve for Tsat by linearly expanding around initial guess Tasat,
we get
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Voltage Glitch Magnitude (VGM)
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To calculate Tasat, approximate the rising part of iseu(t) by a line
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Substitute iseu(t) in Eq. 1 by a line between origin and Imaxseu
Integrate Eq. 1 from Va(t)=0 at t=0 to Va(t)=Vdsat at t=Tasat
Solve for Tasat by quadratic expansion around origin
Now, integrate Eq. 1 with initial condition Va(t)=Vdsat at t=Tsat

Use IDS = K3 + K4.VDS for this integration
(2)
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Voltage Glitch Magnitude (VGM)
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Differentiate Va(t) (Eq. 2) and solve dVa(t)/dt =0
for TVGM
 Linearly expand around Tmaxseu
 Now,
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VGM = Va(TVGM)
If VGM > VDD + 0.6V then set VGM = VDD +
0.6V
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Diode is not modeled in Eq. 2
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Expression for t1
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If VGM > 0.5*VDD then there is a glitch
Substitute t = t1 and Va(t1) = 0.5*VDD in Eq. 2
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Expand linearly around ta1 = TsatVDD/(2Vdsat)
(3)
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Eq. 3 is used to compute t1 for Cases 1, 2 and 3
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Expression for t2 : Case 1
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For Case 1, VGM ≥ VDD+0.6V
Va(t3) = VDD-|VTP|
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IDS of PMOS M2 is zero
iseu (t3) = IDS of M1
Use, Va(t) = VDD-|VTP|
at t = t3 as initial condition
To calculate t3, ignore tb in iseu(t)
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ta is 3-4 times larger than tb
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e-t/tb around t3 will be close to 0
t3
VDD-|VTP|
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Expression for t2 : Case 1
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Model iseu(t) by a straight line for t >t3 between (IDSavg,t3) and
(0, t*)
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TBD what is ids avg
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Obtain t* by equating charge deposited by iseu(t) and the above straight
line model for t >t3
Integrate INV1 output node diff. equation (Eq. 1)
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Initial condition: Va(t) = VDD-|VTP| for t = t3
Substitute Va(t) = 0.5*VDD for t = t2 and solve for t2
 t2a1 is
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the initial guess for t2
Integrate Eq. 1 with IDSVa = IDSVDD+|VTP| and line mode for iseu(t)
Substitute Va(t) = 0.5*VDD for t = t2a1 and solve for t2a1
Closed form exp. of t2a1 is
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Expression for t2 : Case 2
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In this case also, Va(t3) = VDD-|VTP|
Integrate INV1 output node diff. equation (Eq. 1)
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Initial condition: Va(t) = VDD-|VTP| for t = t3
Use original expressions for iseu(t) and IDSVa
Substitute Va(t) = 0.5*VDD for t = t2
Expand around initial guess t2a2 for t2 and solve for t2
Calculate t2a2 by solving equation iseu(t2a2)= IDSVDD/2
 t2a2 >

Tseumax (Time when iseu(t) reaches its maximum value)
Ignore e-t/tb term in iseu(t)
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Expression for t2 : Case 3
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In this case, only M1 conducts
Substitute Va(t) = 0.5*VDD for t = t2 in Eq. 2
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Va(t) equation as shown before
Solve for t2 after expanding around initial guess t2a2 for t2
where
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Now we can calculate the pulse width as t2 - t1
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