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This project in ARM is in
part funded by ICT-eMuCo,
a European project
supported under the
Seventh Framework
Programme (7FP) for
research and technological
development
MPSoC 2009
Targeted execution enabling
increased power efficiency
Anirban Lahiri
Adya Shrotriya
Nicolas Zea
Technology Researchers
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John Goodacre
Director, Program Management
ARM Processor Division
August 2009
Interesting System Configurations…
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Background
Power

Smooth transition between energy
and performance levels

Reduced loss due to leakage
power as cores can be switched off
Addresses the application
performance diversity
Big Core
Power Aware
SMP
Scheduled
Little Core
0.8
0.9
1.0
1.1

Voltage (V)
Fig 1a : Power at Peak performance per Operating Voltage
Power
Power
Big Core
High Performance
Applications
Big Core Tasks
Little Core
Little Core Tasks
Low-power
Applications
Big-Switch
100
200
300
400
700
800
900
1000
MIPS
Fig 1b : Power-Performance Diversity of Single Task Workloads
Disclaimer : The plots are indicative of practical architectures and systems.
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0.8
0.9
1.0
1.1
1.2
Voltage (V)
Fig 1c : Diversity of Multitask Workloads
Analyzing Diversity
Core Executing the Task

Code compatibility (due to
uniform ISA) ensures easy
dynamic task migration (Fig 2a)
Task migration for power
efficiency based on required
performance (Fig 2b). Example
shows a set of tasks T1 – T5

Performance (Avg. MIPS)
Power (mW)
1000
1000
800
800
MIPS 600
600
400
400
200
200
T2
Fig 2a : Single task migrating across cores over time
T4
T4
T2
T3
MIPS
T1
T5
T3
T5
T5
T1
T4
T1
T2

Prevents smaller tasks from
corrupting high performance task
execution. E.g. Task T1 in Fig 2b.

Important to further analyse
temporal effects of SoC power
Time
Fig 2b : Task migrations over time based on
performance requirement in a Multitask Workload
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Power
(mW)
Time
T3
T3
Little Core
Big Core
Methodologies Being Utilized
Flow 1
(High-level Simulation)
System
Generator
Flow 2
(Hardware Emulation)
Flow 3
(Low-level Simulation)
C Code
App / OS
(Parallel / SMP ?)
RTL
ARMCC / GCC
Statistical
Methods
Simulator
RV
Cache
Models
OS - Profiler
On-board
Execution
Netlist
Simulation
(PowerTheater)
Emulator
(Palladium)
Using RVT
Execution
Trace
Cache Hit /
Miss Ratio
OS
Behaviour
Execution
Trace
Power per
H/w Unit
Cache Hit /
Miss Ratio
Power Estimation
Model
Power Estimation
Model
Compare
Accuracy
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Power Estimation
Model
Software Model Considerations
Power Aware SMP
Big-Switch
Level of OS modification
Requires affinity to be
driven by performance
requirement
Potentially no changes
required
Maximum power save
Can operate as bigswitch too
Little and big core need
performance continuum
Level of task diversity
and peak performance
Enable better scalability
Limited to performance
of single CPU
Implementation
complexity
OS needs a speculative
understanding of
performance demands
Invisible to OS, operates
similar to interrupt
service routine
Management
Responsibility
OS performance monitor
Application dependent
Flexibility
SMP / AMP designs
Single CPU only
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Summary Expectations
Power-Aware SMP
Scheduled
Application Scenario
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520mW
Big-Task
(700MIPS)
Big-Core (500mW @ 0.8V)
+ Little-Core (20mW Leakage)
Small-Task
(350MIPS)
Big-Core (50mW Leakage)
+ Little-Core (200mW @ 0.8V)
1 Big-Tasks
+ 3 Small Tasks
(1100MIPS)
Big-Core (500mW @ 0.8V)
+ Little-Core (200mW @ 0.8V)
3 Big-Tasks
+ 5 Small Tasks
(1400MIPS)
Big-Core (750mW @ 1.1V)
+ Little-Core (200mW @ 0.8V)
Big-Switch
Big-Core Only
Little Core Only
Big-Core
(500mW @ 0.8V)
Big-Core
(500mW @ 0.8V)
-
Little-Core
(200mW)
Big-Core
(500mW)
Little-Core
(200mW)
Big Core
(750mW @ 1.1V)
Big Core
(750mW @ 1.1V)
-
-
-
-
250mW
700mW
950mW
Operating Voltage (Volts)
0.8
0.9
1.0
1.1
Possible Power savings up to 50%
Big-Core MIPS at Peak
Frequency
700
800
950
1100
Little-Core MIPS at Peak
Frequency
350
400
450
500
Performance enhancements up to
30% seen by reducing corruption of
high performance tasks
Big-Core Power at Peak
Frequency (mW)
500
575
600
750
Little-Core Power at Peak
Frequency (mW)
200
250
300
350
Key to still understand the costs of
migration
Thank you
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