Transcript DAC Presentation kit

Practical Aspects of Reliability
Analysis for IC Designs
T. Pompl, C. Schlünder, M. Hommel,
H. Nielen, J. Schneider
Purpose
Address practical links between IC design and
reliability of IC operation.
Demonstrate state of the art aspects as well as
future issues.
Direct input of experts working in the field of
process reliability and ESD.
What’s required in EDA tools to
promote design-in reliability?
Outline
Gate oxide integrity
Device reliability
Interconnect reliability
Electrostatic discharge (ESD)
Summary
Gate oxide integrity:
Overshoot events
Each electric stress consumes oxide lifetime;
degradation is cumulative!
Main driver of degradation is the voltage drop
across gate oxide (other driver: temp., active area).
Statistical nature: qualified for e.g. <10 ppm failure
@[Vdd, 10 y, 10 mm2, 100°C].
Voltage overshoot is an additional electric stress.
Analysis of voltage overshoot between any
terminal and gate (guideline: > 10% of Vdd).
Needed: voltage amplitude, duty cycle, device
type, terminals (e.g. gate and drain).
Gate oxide integrity:
New definition of GOX failure criteria
Traditional criterion:
1st soft breakdown (SBD) =
1st irreversible local leakage
path across the gate oxide.
Future criterion:
1st SBD reaching a certain
absolute current level.
log(gate leakage)
log(time)
Dt
log(gate leakage)
log(time)
To be used for ultra-thin SiO2-based oxides; high-k?
Consequences: adds gate leakage and gate noise.
 Digital designs: OK.
 Analog designs: my not tolerate this.
Gate oxide integrity:
New definition of GOX failure criteria
OK for low level SBD
CDF
SBD with low & high
gate leakage level.
This is a worst case
study; realistic is one
SBD.
0.75
0.50
0.25
1.00
0.75
0.50
0.25
high level SBD
low level SBD
no SBD
low level SBD
0.02
CDF
 Up to 8 SBD on/off.
 Device parameter
variation.
CDF
Circuit simulation of NOR gate with
SBD between gate/source and gate/drain.
5000 Monte Carlo runs:
1.00
1.00
0.75
0.50
0.25
1.55
no SBD
fall
rise
high level SBD
0.03
0.04
rise or fall time (ns)
0.05
high level SBD
no SBD
low level SBD
1.60
1.65
1.70
delay between selected output transitions (ns)
Device reliability:
Increasing challenge
Electric field across gate oxide
7
0.065µm
0.18µm
0.35µm
Technology-node
6
EOX [MV/cm]
Process evolution will
lead to higher device
stress.
Reliability safety
margins decreases in
modern technologies.
T13
T12
T11
T10
5
T9
ITRS 2005 - prediction
process development
4
2
4
T8
6
8
EOTelec in inversion [nm]
Circuit reliability is not longer a task only for technology development but also for circuit designers.
Designers have to be supported by smart software tools with build-in reliability know how!
10
Device reliability:
Full-custom design
voltage (V)
Reasonable for relatively low numbers of transistors
(analog / RF circuits).
Circuit simulators with built-in reliability can simulate
entire circuit blocks.
Based on models
parameter degradation
for each device can be
calculated.
Designers can access
fresh
1y 10y
each device
characteristic to optimize
200 ps
the circuit.
time (ns)
Device reliability:
Constrains for semi-custom design
For digital applications a more automated design
approach is used.
Library elements are placed automatically.
Designers don’t know in advance where a single
element is placed. No direct access.
Thus, it’s difficult to manually determine reasonable
operation conditions for single library elements.
A single library element is used in many different
sub-circuits, and within, is exposed to a lot of
different applications/operation conditions.
For all of these combinations a delay-calc. would be
necessary, since digital design is delay driven.
Device reliability:
On-chip variation (OCV) approach
In semi-custom design a completely different
approach is necessary.
A possible consideration: calculation of parameter
degradation as a part of OCV.
Stress-induced parameter variation can be
transformed in propagation-delays.
Smart software tools can
check time paths.
In the case of time
conflicts, gates can be
replaced by faster ones,
but this consumes area
& power.
Tsetup
Thold
CLK
D
Q
CK
logic
D
Q
CK
Interconnect reliability:
Critical layout structures
Electromigration
 Single vias connected to …
 Wide metal lines with …
 Current flow in downstream direction.
Stress-induced voiding
 Single vias connected to …
 Wide metal plates or slitted plates.
Breakdown of Inter-metal dielectric
 Metal lines with minimum pitch, operated at …
 Maximal potential difference of neighbored lines.
Interconnect reliability:
Analysis of critical structures
8,0E+07
6,0E+07
4,0E+07
2,0E+07
128.8 mm²
70.6mm²
54 mm²
40 mm²
25 mm²
single Via5
single Via4
0,0E+00
single Via3
 duty cycle of
operation
 temperature
 …
1,0E+08
single Via2
Other operation
conditions:
Single Contacts, Vias
single Via1
 DC-current density
 DC-pulses
 AC-current
Example for geometrical
analysis
single CA
Geometrical
dimensions.
Electrical operation
conditions:
Interconnect reliability:
EM – Influence of geometry
EM life time as function of line width for a single
via down-stream structure
w
t-50 [a.u.]
lot 1
lot 2
mininimum
design width
0,0
0,1
0,2
0,3
0,4
0,5
w [µm]
EM life time is limited by single vias on wide lines.
By avoiding these structures higher current
densities could be used for product design.
Interconnect reliability:
SIV – Influence of geometry
Life time of stress-induced voiding (SIV) as function
of line extension length L
MTF [hrs]
1000
L
100
0
L
0,5
1
1,5
Line extension length L [µm]
2
Increasing the distance of the single via from the
plate increases the SIV life time.
Electrostatic discharge (ESD)
ESD represents a major threat to ICs.
Standard ESD specifications
 Human Body Model (HBM)
 Pre-charged human being touches IC.
 Vcharge = 2 kV, corresponding to Imax ~ 1.3 A, pulse width
of 150 ns.
 Charged Device Model (CDM)
 Pre-charged IC discharges via one pin.
 500 V, Imax ~ 10-20 A, pulse width 1-2 ns.
ESD damage
 Melting in silicon (diffusions of MOS devices, diodes,…).
 Breakdown of gate oxides.
Electrostatic discharge:
ESD and IC design
Lots of ESD rules to be
followed…
 Special diodes D1, D2 in
place.
 Power clamp ggnmosESD
in place.
 Output drivers N1, P1 must
follow ESD layout rules.
 N1, P1 must match to the
supply voltage at VDD.
VDD
D1
P1
Out
D2
N1
ggnmosESD
VSS
2 types of rules
 DRC like: standard DRC tools with ESD marking layers.
 Net-oriented: in-house tools for circuit analysis.
Electrostatic discharge:
Design rule check (DRC)
Detect ESD relevant areas via ESD layer.
Recognize layout of diodes, MOS devices, SCR, …
Example: drain contact-to-gate spacing aD with
silicide blocking.
D
S
aD
sal. block
Requires some awareness of layouter.
Better: parameterized ESD cells.
Electrostatic discharge:
Net-oriented rule checking
Idea: extract netlist from layout and check ESD rules
 Like LVS, take ESD marking layers into account.
 Information on pin types needed, e.g. supply voltages.
 Can also be realized on pre-layout netlists.
Rule types
 Existence and connectivity of ESD devices.
 Matching of device classes and supply voltage classes.
Examples:
 Thin oxide device between
power domains (not allowed).
 Thin oxide cap. at VDD/VSS.
 Existence of correct power
clamps.
VDD1
VDD2
thin oxide
detected
devices
thin oxide
VSS
Electrostatic discharge:
ESD awareness of future EDA tools
ESD DRC is OK with existing DRC tools.
No commercial tools for net-oriented ESD rules
available.
 Should be imbedded in design flow.
 Need for infrastructure: ESD pin types, power domains,
ESD endangered interfaces.
 Also for pre-layout-synthesis checks.
 Should work on data of a whole IC.
Tool for IR-drop analysis of ESD pulses.
 Find bad metallization, ESD endangered positions on
IC,…
Auto-placement of ESD cells according to some
formalized guidelines would be great!
Summary
Gate oxide reliability
 Identify voltage overshoot events.
 New gate oxide failure criteria to be considered.
Device reliability
 Increasing electric field; NBTI becomes design issue.
 Simulation using degraded devices: constraints for
semi-custom design
OCV approach.
Interconnect reliability
 Control via placing to improve EM & SIV.
 Identify metal line with minimal pitch (TDDB risk).
ESD
 Net-orientated ESD rules, IR-drop analysis.
 Automated placement of ESD and I/O cells.