Transcript Chip level EMC measurements and simulations COST 286

Slide 1
Chip level EMC measurements and
simulations
“Impact of Communications Technology to EMC“,
COST 286 Workshop
Vladimir Čeperić
Hrvoje Marković
Adrijan Barić
Faculty of Electrical Engineering and Computing,
University of Zagreb
Split, 12 December 2005
University of Zagreb
Chip level EMC measurements and simulations
Slide 2
• European research program ROBUSPIC (ROBUst mixed signal design
methodologies for Smart Power ICs).
• UZAG’s focus points:
–
Development of parasitic extraction procedures suitable for EMC
(electro-magnetic compatibility) analysis
–
Identification and modelling of EME (electro-magnetic emission)
sources and analysis of EMI (electro-magnetic immunity)
–
Methodology for full-chip smart-power EMC simulation
Split, 12 December 2005
University of Zagreb
Outline
Slide 3
• Integrating EMC simulations in design flow
• Extraction and influence of PWR/GND parasitics
• EMC measurements system (IEC 62132-4 and IEC 61967-4)
• EMC test chip
• EMC optimizations
• Conclusion
Split, 12 December 2005
University of Zagreb
Design flow
System level architecture design
& component spec.
PWR/GND lines/core
of the circuit
separation
Electrical circuit design
RC extraction of the
core (Assura, ...)
RC (RLC) extraction
of PWR/GND lines
Physical pattern layout
MOR
RC/RLC parasitic extraction &
EMC simulations
Measurement & verification
Spice netlist
EMC simulations
Split, 12 December 2005
University of Zagreb
The influence of the PWR/GND parasitics on the the
emission levels
Slide 5
Comparison of invertor module and invertor module with HFSS extracted PWR/GND structure
Split, 12 December 2005
University of Zagreb
Influence of the package
SOIC8 package
NEED TO CONSIDER PACKAGING PARASITICS!
Split, 12 December 2005
University of Zagreb
Slide 6
Cadence Interface in Skill language
For conducted EME (IEC 61967-4)
- automatic generation of the Spectre netlist(s) with implementation of the 1
Ohm
method
- transient simulations in Spectre
- manipulation of the results to determine the spectrum
- display of the results and automatic determination of the emission levels
For EM immunity (IEC 62132-4)
- Spectre analyses for defined
input power range
- determination of the input power
which causes malfunction
- display of the results
Split, 12 December 2005
University of Zagreb
Slide 7
IEC 62132-4 for the measurement of EM immunity with direct
RF power injection method - HTVD LIN
RC load of the BUS, R=1 kOhm (to VBAT) and C=1 nF to GND
Operating at 20.0 kbit/sec, VBAT = 13.7 V,
Input frequency f=1 MHz
Split, 12 December 2005
University of Zagreb
EMC measurement system
Slide 9
EME and EMI HTVD LIN interface measurement system
Split, 12 December 2005
University of Zagreb
HTVD – LIN interface EMC measurements
Slide 10
EME measurements-
Voltage over 1 Ohm
(IEC 61947-4)
– Matlab measuring automatization:
– EME_EMI_measure_GPIB.m script
BUS
TxD
RxD
Split, 12 December 2005
EMI measurements - DPI method (IEC 62132-4)
University of Zagreb
HTVD – LIN interface 1 Ohm method
measurement
Split, 12 December 2005
simulation
University of Zagreb
EMC test chip
Slide 12
Chip for EMC testing:
high voltage and low voltage parts - ams C35/H35
digital
conducted EME testing structure (to evaluate the influence of
backannotation)
LIN interface (conducted EME and EMI)
analog
LC oscillator (conducted EME, package parasitics model evaluation)
Split, 12 December 2005
University of Zagreb
EMC test chip
Slide 13
Chip for EMC testing:
two different packages used to
evaluate package influence on EME
and EMI
CLCC84
(Ceramic Leadless Chip Carrier)
JLCC84
(J-Leaded Ceramic Chip Carrier)
Split, 12 December 2005
University of Zagreb
EMC test chip
Slide 14
Chip for EMC testing:
conducted EME
testing structure
LIN1, LIN2
LC oscillator1,
LC oscillator2
Split, 12 December 2005
University of Zagreb
Conducted EME testing structure
Conducted EME test structure enables:
1.
Independent switching of 96 blocks
2.
Input of each block can either be common input signal or
output of previous block
3.
Different widths of PWR/GND rails
4.
Different number of PWR/GND refreshes
5.
Output buffers with different output currents can be enabled
Split, 12 December 2005
University of Zagreb
Slide 15
QUAD LC oscillator and VCO
•
•
•
•
•
High voltage (AMS H35 CMOS technology)
Cross-coupling increases significantly the precision of the oscillation
frequency
Bond wires provide a resonant tank with high Q
conducted EME simulation and measurement
Bond wires used as inductance
– package parasitics model evaluation
VCO
Split, 12 December 2005
University of Zagreb
Slide 16
LIN interface
Slide 17
• LIN interface is design in high voltage technology (50V)
• Design is tested for EM emission and EM immunity
LIN interface from LIN2.0 standard ( Figure 3.1 )
Split, 12 December 2005
University of Zagreb
LIN interface EME optimization
– Matlab script: EmissionLeveloptimization.m
Before optimization: C-10-o
After optimization: C-12-m
Optimization parameters: voltage levels on BUS, emission level of LIN interface,
width, length and number of fingers of the high voltage transistor at TxD input
Split, 12 December 2005
University of Zagreb
LIN interface EMS optimization
Matlab script: ImmunityOptimization.m
• Psin source connected to BUS pin via 4.7nF capacitor
f1=150kHz, f2=1MHz, dBm=20
Without optimization:
With optimization:
max: td1=6.0755e-06, td2=5.691e-06
max: td1=5.2535e-06, td2=5.691e-06
duty cycle min=0.4098
duty cycle min=0.4278
0.42793
Optimization parameters: duty cycle and time delay (LIN 2.0 standard),
duty cycle max=0.4254
duty cycle max=
width, of the 10 transistors in Schmitt trigger
Split, 12 December 2005
University of Zagreb
Conclusion
Slide 20
• EMC simulations can be incorporated into design flow
• Package and PCB parasitics have to be considered
• EMC measurement system according to IEC 62132-4
and IEC 61967-4 standards is being built
• EMC test chip enables easy validation of EMC
simulations vs. measurements
– package model validation
– comparison of 3D EM simulations vs. RC extraction
simulations
• Circuit optimizations wrt. EMC behavior are performed
Split, 12 December 2005
University of Zagreb