Transcript ENGG 3640: Microcomputer Interfacing

ENG3640
Microcomputer Interfacing
Week #9
Serial Communications
Topics
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Serial I/O Background
Asynchronous Communications
The SCI Interface
Synchronous Communications
The SPI Interface
SPI Topologies and Applications
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Resources
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Huang, Chapter 9, Sections
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9.1 Objectives
9.2 Fundamental Concepts of Serial Communication
9.3 The RS-232 Standard
9.4 The 68HC12 Serial Communication Interface
9.5 Interfacing SCI with EIA-232
9.6 The SCI Operations
Huang, Chapter 10, Sections

10.1 – 10.5 HC12 SPI System
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1-KB SRAM
68HC812A4
Block
Diagram
4-KB EEPROM
CPU12
Port AD
Analog to Digital
Port T
Timer Module
Port S
Serial
Communication
I/O Ports
I/O Ports
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Parallel and Serial Transmission
Two types of transmission are widely used today:
Parallel Transmission (busses)
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
1.
2.
Data is transmitted in one pulse (fast)
Usually used for short distances (Why?)
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

Bulky and expensive (many I/O lines).
Susceptible to reflection and induced noise.
Many I/O devices do not have a high enough data rate to justify
the use of parallel data transfer.
Serial (RS-232, USB)

1.
2.
3.
4.
Serial by bit (slow)
Each bit takes one pulse
Generally used for longer distances
Cheap
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The Serial I/O Port
The port contains a bus
interface through which
the microprocessor can

1.
2.
3.
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Send commands to the
port.
Read port status
Access input/output data
registers in the port.
What distinguishes this
port from the general
structure of an I/O port is
the conversion that occurs
between serial and
parallel data streams.
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Serial I/O Background

Transmitter encodes a data signal to be sent to the receiver.


The receiver samples the serial signal to detect/decode the data.


The timing of the data signal is based on the transmitter clock fT
The timing of the receiver sampling is based on a receiver clock fR
In order to catch every data bit the receiver sampling times
must be synchronized to the transmitted signal in some way!

Synchronization techniques: (a) Synchronous (b) Asynchronous
Serial Communication Link
Transmitter
Receiver
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Modes of Channel Operation
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Transmission is unidirectional.
Usually called receive only
transmission.
Example TV, Radio, PC  Printer
Transmission is possible in both
direction but not at the same time.
People communication in halfduplex.
EX: Multiple computers connected
together talking
Full Duplex allows information
(data) to be transferred
simultaneously in both directions.
EX: Standard Telephone.
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Traditional Configurations
Host communicates with the
terminals using a dedicated link.
Terminals can communicate with
each other via host only.



Host communicates with the
terminals using a shared
connection.


Other Topologies?

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Terminals have to identify if data is
intended to them (address)
Star, Mesh, Ring
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The Serial Subsystems
MCU12 has 2 subsystems for serial interfacing

I.

II.



An Asynchronous Serial Communication Protocol:
The serial communication interface (SCI) that can be used
to connect a terminal or personal computer to the
microcontroller (used in our EVB Boards)
A Synchronous Serial Communication Protocol (SPI):
The serial peripheral interface (SPI) can provide highspeed serial communication to peripherals or other
microcontroller units
Proposed by Motorola to facilitate the data exchange
between microcontrollers and peripheral devices.
Similar protocols: I2C (Philips), Micro-wire (National Semi)
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I. Synchronous Serial Communication
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
Synchronous communication systems always transmit a clock signal
with the data to synchronize the receiver to each bit time.
The clock is provided as a separate clock signal or it can be
embedded in the data signal itself.
Transmitter
Receiver
CLK
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Principle Binary Codes
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There are many ways to
encode data (i.e. identify
marks (1) and the spaces (0)).
1.
NRZ
2.
NRZI
3.
RZ
4.
CMI
5.
Manchester
6.
Diff Manchester
They are called coding types
or modulation formats.
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I. Synchronous Serial Communication

The clock is provided as a separate signal or it can be
embedded in the data signal itself.
 Two common ways to embed a clock into the data signal
are to use (i) Manchester or (ii) variable pulse width
signaling.
 Notice signal change in middle of every bit  used by
receiver to synchronize the sampling process.
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Manchester Data Encoding
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Synchronous: Separate Clock Signals
Other synchronous serial communication systems send the
synchronization clock as a separate clock signal.
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
The clock’s rising edge always falls in the center of the data bit time.
Examples: Motorola SPI, Phillips I2C, National MicroWire.
The advantage of using a separate clock:
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1.
2.
Circuit Simplicity (rising edge triggered shift register)
Data rate does not have to be fixed
The disadvantage?
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1.
A Separate clock signal is required (long distance, expensive, reliability!)
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II. Asynchronous Serial Communication

Each device uses its own clock.
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
The clocks must run at the same rate but do not need to be
synchronized.
The receiver clock must be within 4% of the transmitter clock.
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UART :
Universal Asynchronous Receiver Transmitter.
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The UART is the interface
chip that implements serial
data transmission.
Also known as (ACIA)
asynchronous
communication interface
adapter.
If you need more serial ports
you would use an UART to
interface with your MCU.
Six major components:
1.
2.
3.
4.
5.
6.
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Chip select & read/write cont
Data bus buffers
Transmit data Register
Receive data Register
Status Register
Control Register
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Asynchronous Data Frame

The basic unit of information is the character or data
frame
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A Frame is a complete and non divisible packet of bits.
• It includes both information (data) and overhead (extra bits)
Synchronization is achieved using Start-Stop bits.

i.e. the receiver needs to know when a character starts and when it
stops => character is framed by start and stop bits
Idle time
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Start and Stop Framing. Parity
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The transmitter can send characters at any rate, so there
may be delays between the transmission of each
character
The receiver detects the falling edge of the start bit and
then attempts to sample in the center of each bit time.
Parity is used to detect single bit errors
 type: even or odd
 the quantity of 1 bits in the data determine the parity bit
The receiver also needs to know (i) number of data bits
in each character, (ii) type of parity used if any, (iii) number
of stop bits.
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Start, Stop and Parity Bits
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Example

The letter `A’ is to be transmitted in the format
with (i) 8 data bits (ii) no parity (iii) one stop bit
Sketch the output

The ASCII code for `A` is $41 or %01000001
1
0
0 0
0
0
1 0
LSB
Idle
Stop Bit
Start Bit
LSB
MSB
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Example: Using RS-232
+15V
time
0V
Using RS-232
-15V
1
0
0 0
0
0
1 0
Idle
Stop Bit
Start Bit
LSB
MSB
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Example
Show the framing bits when the char B (21)16
is sent at 7 data bits, 2 stop bits, odd parity:
Solution:
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
1.
2.
3.
4.
start bit: 0
data bits: 0100001
parity bit: 1
stop bits: 11
1 0 0 0 0 1 0
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Data Speed, Baud
Two units of speed are employed in data
transmission.
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1.
2.
For a binary two-level signal, a data rate of one bit
per second is equivalent to one Baud.
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# of data bits transmitted per second (BPS)
Baud : the rate at which the signal changes
if a data transmission system uses signals with 16 possible
discrete level, each signal can have 16 = 24 different values
(i.e., signal element encodes 4 bits)
Example: If the 16-level signals are transmitted at 1,200
Baud, the data rate is 4 x 1,200 = 4,800 bps.
Effective BPS = (nr of data bits)/(nr of frame bits) x
baud
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Example
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How long does it take to transmit one character at a
speed of 9600 bauds? Each character is transmitted
using a format of seven data bits, even parity, one stop
bits.
Solution:
1. Each character consists of 10 bits (1 start, 1 stop, 1
parity, 7 data)
1.
2.
3.
Effective Data bit rate: 7/10 x 9600 = 6720 BPS
Each bit requires 104 uS = (1/9600)
Thus each character will require
10 x 104uS = 1.04 mS
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The RS-232 Standard

The RS-232 standard was established in 1960 by the
Electronic Industry Association (EIA) for interfacing
between a computer and a modem.
 The standard is referred to as either




RS-232 or
EIA-232
In data communication terms, both computers and
terminals are called data terminal equipment (DTE).
Modems and routers are called Data Communication
Equipment (DCE)
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Data Communications Interfacing
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Modems
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Modems is a contraction
of modulator-demodulator
Modem is used to send
and receive serial
digital data over a
telephone line
Basics of modems
Modem is connected to a
serial port

dedicated circuit
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
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the serial port, the RS-232
data terminal equipment
(DTE) -> connected to a
modem, a data
communication equipment
(DCE) -> to a telephone line
Transmission ...
Receiving ...
The audio signal is known as
the carrier signal
Tech: PSK; DPSK; QAM
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Carrier Modulations (Analog)
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Carrier Modulations (Digital)
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Differential Phase Modulation

Phase is shifted by multiples of 90, therefore
two bits at a time can be transmitted.
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The RS-232 Standard
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1.
2.
3.
4.
There are four aspects to the EIA-232 standard
Electrical specifications -- specifies the voltage level, data rates,
distance of communication
Mechanical Specifications – specify the number of pins and the
shape and dimensions of the connectors.
Functional Specifications – specify the function of each signal.
Procedural Specifications – specifies the sequence of events
for transmitting data
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(1) The EIA-232 Electrical Specs
The interface is rated at a signal rate less than
20 KBPS. With good design, however, we can
achieve a higher data rate.
The signal can transfer correctly within 15
meters. Greater distance can be achieved with
good design.
Driver maximum output voltage is -25V to +25V
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A voltage more negative than -3V at the receiver’s
input is interpreted as logic one.
A voltage more positive than +3V at the receiver’s
input is interpreted as logic zero.
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(2) The EIA-232 Mechanical Specs
RJ45 (EIA-561) Connector
V.24/RS-232 DB25 Pin Connector
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DB9 (EIA574) Connector
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Cont .. Mechanical: The EIA-232
Cable
The simplest RS232 cable uses just :
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TXD,
RXD and
Ground with optional ground shield.

The shield provides protection from electric field interference.
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(3) Functional Specs
I.
II.
III.
IV.
V.
VI.
VII.
VIII.
DTR (Data Terminal Ready) (DTE)
DSR (Data Set Ready) (DCE)
RTS (Request to Send) (DTE)
CLS (Clear to Send) (DCE)
RI (Ring Indicator) (DCE)
TX (Transmit)
RX (Receive)
….
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Cont … Functional Specs
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Procedural Specification
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E.g. Asynchronous private line modem (Pointto-Point Link ``Not over the phone line” )
The modem will require only the following
signals to operate:
1.
2.
3.
4.
5.
6.
GND,
Tx, Rx,
RTS, (Request to Send)
CTS, (Clear to Send)
DSR, (Data Set Ready)
DCD (Data Carrier Detect)
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Computer
(DTE)
Tx
Rx
DCD
Tx
Rx
DCD
CTS
CTS
RTS
DSR
GND
Modem
(DCE)
Modem
(DCE)
Direct link
RTS
DSR
GND
Tx
Rx
DCD
CTS
RTS
DSR
GND
Computer
(DTE)
Tx
Rx
DCD
CTS
RTS
DSR
GND
Tx: transmit data
CTS: clear to send
Rx: receive data
RTS: request to send
DCD: data carrier detect DSR: data set ready
Figure 9.2 Point-to-point asynchronous connection
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(2) Functional/Procedural Specs
I.
II.
III.
IV.
V.
VI.
VII.
VIII.
DSR (Data Set Ready)  From DCE (i.e., Modem is ready)
RTS (Request to Send)  DTE to DCE (i.e., DTE Wants to send info)
CLS (Clear to Send)  ACK from DCE (i.e., Data may be transmitted now)
Local Computer (i.e., DTE) sends data serially to modem.
Local Modem (i.e., DCE) modulates signal but before that sends a carrier
signal to remote modem.
Remote Modem detects the carrier signal ring and asserts DCD to inform
remote DTE that a call arrived.
DCD (Data Carrier Detect)  Remote Modem (i.e., DCE) indicates that a
carrier frequency has been established.
Remote Modem (i.e., DCE) receives modulated data, demodulates it and
sends it to remote DTE.
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Sequence of events occurred during data transmission over dedicated link
Time
Local
Remote
1. DCE asserts DSR
2. DTE asserts RTS
3. DCE asserts CTS
4. DTE starts to send
data (to local DCE)
5. DCE sends out a
carrier and then the
modulated data
6. DCE asserts DCD
7. DTE waits for
arrival of data
8. DCE sends out
demodulated
received data
9. DEC receives
demodulated data
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Procedural Specification

Over the telephone line the modems will have
to go through the following phases:
1.
2.
3.

Phase 1: Establishing the Connection
Phase 2: Data Transmission
Phase 3: Disconnection
The modem will require more signals to
operate: GND, Tx, Rx, RTS, CTS, DSR, DCD,
…..
Computer
(DTE)
Tx
Rx
RING
DCD
CTS
RTS
DSR
DTR
GND
Modem
(DEC)
Tx
Rx
RING
DCD
CTS
RTS
DSR
DTR
GND
Modem
(DEC)
Phone line
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Tx
Rx
RING
DCD
CTS
RTS
DSR
DTR
GND
Figure 9.3 Asynchronous connection over public phone line
Computer
(DTE)
Tx
Rx
RING
DCD
CTS
RTS
DSR
DTR
GND
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Sequence of events occur during data transmission over public phone line
time
Local(transmission side)
Remote (receiving side)
Connection
establishment
phase
1. DTE asserts DTR
2. DCE dials the
phone number
3. DCE detects the ring
and asserts RING
4. DTE asserts DTR
to accept the call
6. DCE asserts DSR
and DCD and also
sends out a carrier
for full duplex
operation
5. DCE sends out a
carrier and asserts
DSR
7. DCE asserts DCD
(full duplex operation)
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Sequence of events occur during data transmission (continued)
time
Local(transmission side)
Remote (receiving side)
Data
transmission
phase
1. DTE asserts RTS
2. DCE asserts CTS
3. DTE sends out
data to DCE
4. DCE modulates data
and sends it out
5. DCE demodulates
data and forwards
the data to DTE
6. DTE receives
data
Disconnection
phase
1. DTE drops RTS
2. DCE drops CTS
and drops the carrier
3. DCE deasserts
DCD & DSR
4. DTE deasserts
DTR
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RS-232 Interface Standard: Summary


Equipment using
asynchronous serial com.
normally use the RS-232
interface
The logic levels used for RS232 signals are:







Many signals are not used =>
serial ports also use a DB-9
connector
Common signals:


+12 V for logic 0;
-12 V for logic 1


This is to allow signals to be
transmitted over greater
distances
This is a bipolar form of NRZ
format
The standard defines 25
different signals






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Transmit data: TxD or TD
Receive data: RxD or RD
Request to send: TSR
Clear to send: CTS
Data set ready: DSR
Signal ground: SG
Data carrier detect: DCD
Data terminal ready: DTR
Ring indicator: RI
From normal HCMOS and TTL
levels we need to use special
driver chips for ...
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Null Modem



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The EIA standard
doesn’t allow for a
direct connection
between two DTEs
When two DTEs wish
to communicate then
we have to use a DTEDTE null modem cable
configuration.
The Null Modem
fools both DTEs into
thinking that they are
connected to
modems.
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RS422



To increase the baud rate and maximum distance, the
balanced differential line protocols were introduced.
RS422 signal is encoded in a differential signal A-B
because each signal requires two wires
RS422 can connect one transmitter to 10 receivers.
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RS232 vs. RS422
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The Serial Communication Interface
(SCI) in 68HC12
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

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With additional conversion
circuits the SCI can be used
to communicate with remote
devices
SCI uses port S pin PS1 as
TxD and PS0 as RxD
These lines can be enabled
or disabled by one of the SCI
control registers (SCCR2)
When enabled SCI
subsystem has control of the
respective port S lines and
overrides DDRS settings

Transmitting is a simple
matter of writing bytes to a
data register SCDR


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the SCI handles the
framing requirements
(no parity)
The SCI receiver
automatically changes each
framed serial character into a
byte
BAUD register is used to
configure the clock
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SCI Block Diagram
Transmit/Receive
through S0,S1 or S2, S3
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Simplified Functional Block Diagram of the SCI
Consists of:

1.
2.

A transmit data register (SC0DRL) that acts as a buffer
A 10 or 11-bit shift register
When a byte is written to SC0DRL, that byte along with Start bit, Stop bit
and optionally a Parity bit is transferred to the transmit shift register.
Transmitter
Receiver
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SCI Control and Status Registers
Control
Status
Data
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Configuring the SCI
Several steps have to be taken to configure
the SCI sub module within the MCU12

1.
2.
3.
4.
5.
Setup the baud rate
Setup the operating mode
Enable the appropriate interrupts
Transmitting SCI Data
Receiving SCI Data
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(1) Baud Rate Generation
The first step in configuring the SCI is to set the baud rate
There is a standard set of baud rates for asynchronous
communication systems, most notably, 2,400, 4,800, 9,600 bps.
The baud rate is controlled by the bits SBR12-SBR0
SCI Baud Rate (transmitter) = fP/(16.BR)







BR is the value stored in SBR12-SBR0
fP is the frequency of the MCU P-clock
P-clock is an internal MCU clock that has the same frequency as the Eclock FXTAL/2 but is 90 out of phase
SBR12 SBR11SBR10 SBR9 SBR8
SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
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Baud Rate Register Setting

I.
II.
III.
The table shows the required baud-rate register setting
for standard baud rates and a Module Clock of 10.2
MHz.
The baud rate divisor is
the value written to the
SBR12-SBR0 bits
The receiver clock
frequency is the MCLK
divided by the baud rate
divisor.
The transmitter clock
frequency is the receiver
clock frequency divided
by 16.
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SCI Control Register SC0CR1
The second step in configuring the SCI is to set up the
operating mode by loading a value into the first SCI control register,
SC0CR1.

1.
2.
3.
4.
5.
LOOPS: Loop mode bit (0=Normal Mode, 1= Loop Mode)
M: Mode bit (0 = Normal 8-bit mode, 1 = 9-bit mode)
WAKE: Wake-up Mode (0=Wake up by idle line, 1= WU 9th bit)
PE: Parity Enable Bit (0= No Parity, 1 = 9th bit used for parity)
PT: Parity Type (0=Even Parity, 1=Odd Parity)
LOOPS
M
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WAKE
PE
PT
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SCI Status Registers: SC0SR1/SR2
The progress of the transmitter/transmitter can be determined by
several flags in SC0SCR1/SC0SCR2 registers
Transmitter:


1.
2.
TDRE: Transmit Data Register Empty Flag (Set after the data have been
transferred to the shift register)
TC: Transmit Complete Flag (Set when the shift register completes
shifting out the data)
TDRE
TC
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Example
Example 9.4 Write a subroutine to output the character in accumulator A to the SCI0
channel using the polling method.
Solution:
- The subroutine will wait until the bit 7 of SC0SR1 register is set before sending out the
character in accumulator A.
#include "d:\miniide\hc12.inc"
putc_sc0 brclr
SC0SR1,$80,*
staa
SC0DRL
rts
; wait for TDRE to be set
; output the character
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SCI Status Registers: SC0SR1/SR2

Receiver:
1. RDRF: Receive Register Full Flag (Set when a
character is received and transferred into SC0DRL,
Data Register)
2. IDLE: Idle Line Flag (Set when an idle line is detected)
3. RAF: Receiver Active Flag (Set when a character is
being received)
RDRF IDLE
RAF
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Example
Example 9.5 Write a subroutine to read a character from the SCI channel 0 using the polling
method. The character will be returned in accumulator A.
Solution: Assembly function is as follows:
#include "d:\miniide\hc12.inc"
getc_sc0
brclr
ldaa
rts
SC0SR1,$20,*
SC0DRL
; wait until RDRF bit is set
; read the character
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Error Types
Several errors may occur during transfer
using asynchronous serial transmission:

1.
2.
3.
4.
Framing Error.
Receiver Overrun Error.
Noise Error.
Parity Error.
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Framing Error Example
A Framing Error
occurs when a
received character is
improperly framed by
start bit or stop bits.



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It is detected by the
absence of the stop
bit.
It indicates
synchronization error
and faulty
transmission.
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Overrun Error


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A receiver overrun error
occurs when one or more
characters in the data
stream are lost.
The characters are usually
received but not read from
the buffer (i.e., shifted but
cannot be loaded into the
receive register because it
is already full!!)
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Noise Error



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The receiver uses a
sampling clock that
has a frequency of
16 times the baud
frequency.
Once the receiver
has established the
bit boundaries, it
samples the bits
during the 8th, 9th,
and 10th cycles of
the sampling clock.
If the samples are
not identical then a
noise error occurred.
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SCI Status Registers: SC0SR1/SR2

1.
2.
3.
4.
Receiver:
OR: Overrun Flag (Set when a character is shifted into the
receiver but cannot be transferred because the receive register is
already full)
NF: Noise Flag (Set when noise is detected by receiver)
FE: Framing Error Flag (Set when a zero is detected during the
Stop bit time.
PF: Parity Error Flag (Set when the incorrect parity is detected by
rec.
OR
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FE
PF
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SCI Control Register SC0CR2
The third step in configuring the SCI is to enable appropriate interrupts
by loading a value into the second SCI control register, SC0CR2.

1.
2.
3.
4.
TIE: Enables TDRE flag (Trans DR Empty) to generate interrupt request.
TCIE: Enables TC flag (Trans Complete) to generate interrupt request.
RIE: Enables RDRF flag (Receive DR Full) to generate interrupt request.
ILIE: Enables IDLE flag (Idle Line ) to generate interrupt request.
TIE
TCIE
RIE
ILIE
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SCI Control Register SC0CR2

1.
2.
The fourth step in configuring the SCI is to enable the SCI Transmitter
and Receiver
TE: Enables the SCI Transmitter and Configures the TXD pin
RE: Enables the SCI Receiver.
TE
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SCI Driver Routines
; ----------------------------------------------------------------------------------------------;
SCI_OPEN  Initializes SCI
;
Normal 8-bit mode, 9600bps, no interrupts
;-----------------------------------------------------------------------------------------------SCI_OPEN movw #52, SC0BD
; 9600bps @ 8MHz Eclk
movb #$00, SC0CR1 ; Normal 8-bit mode, no parity
movb #$0C, SC0CR2 ; No ints enable transmitter, receiver
rts
;----------------------------------------------------------------------------------------------;
SCI_READ  Read SCI
;
returns ACCB = char or 0 if no char has been received
;----------------------------------------------------------------------------------------------SCI_READ clrb
brclr SC0SR1, RDRF, SCI_READ
; get status
ldab SC0DRL
; get data
rts
;----------------------------------------------------------------------------------------------;
SCI_WRITE  Write to SCI
;
Outputs the character passed in ACCB
;----------------------------------------------------------------------------------------------SCI_WRITE brclr SC0SR1,TDRE, SCI_WRITE
; wait for TDRE
stab SC0DRL
; send data
rts
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Synchronous Serial I/O Subsystem

The SPI (Serial Peripheral Interface) consists of a clock
driven by the Master, MISO (Master In Slave Out), MOSI
(Master Out Slave In) and Slave Select Pin (SS)
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SPI Configuration

To configure the SPI, we need to
1. Set the baud rate
2. Configure the SPI clock format
3. Set the data mode
4. Set the pin direction in the data direction register for
PORTS.
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Synchronous Serial I/O Subsystem
The HC12 uses bit 7, 6, 5 and 4 of PORT S for its SPI data lines.
If a pin of PORT S needs to be set up as output in order to use the
HC12 SPI, you need to write a 1 to that bit of the DDRS.





In Master Mode, you need to write a 1 to bit 7, 6, 5.
In Slave Mode, you need to write a 1 to bit 4 (MISO)
You should setup DDRS before you set up the SPI Control Registers
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Synchronous Serial I/O Subsystem



Each SPI module has an 8-bit shift register connected to the SPI
data register (SP0DR).
The synchronization clock is always generated by the master.
When data is written to the Master SP0DR register, the SPI shifts
the 8-bits out of the MOSI pin while shifting in 8-bits from the MISO
pins
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Slave Select Line



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A Master HC12 can talk with
more than one slave HC12’s
A slave uses its Slave
Select (SS) line to
determine if it is the one the
master is talking with.
There can only be one
master HC12, because the
master HC12 is the device
which generates the serial
clock signal.
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Using SPI With Other Devices
The HC12 can communicate with many type of devices
using its SPI



For example, a Digital-to-Analog Converter.
The D/A converter has three digital lines connected to the HC12
(Serial Data, Serial Clock, Chip Select)
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Using SPI With Other Devices
The HC12 can talk to a Real Time Clock (RTC)





An RTC keeps track of the time (year, month, day, …)
An RTC can be programmed to generate an alarm (interrupt) at a
particular time
The HC12 initially tells the RTC what the time is
The RTC keeps track of time from then on.
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Comparison of Sync Serial Comm
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Summary

The main drawbacks of using parallel data transfer:




Serial communications comes in two flavors



Requires many I/O pins
Many I/O devices do not have high enough data rate to
justify the use of parallel data transfer
Cost is high and limited distance
Asynchronous mode (RS-232, EIA-232, RS-442, ….)
Synchronous mode (requires clock signal)
The main characteristics of asynchronous serial
communications (RS-232)




Data rate is 20Kbps
Signal can transfer correctly within 15 meters
Driver max output voltage is -25V and +25V
A voltage more negative than -3V is interpreted as 1.
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Manchester Data Encoding





A Clock extraction circuit is based upon a phase-locked loop (PLL)
A VCO initially runs at a frequency close to the expected data rate.
The phase detector compares the phase of VCO with incoming data.
When not in phase an error proportional to frequency difference adjusts
the VCO to match or lock to incoming data signal
Reciever has now the capability of timing its decision circuit at exactly
the rate of the data and in the center of the bit period.
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(4) Procedural Specification
E.g. Asynchronous private line modem
When turned on and ready, modem (DCE) asserts
DCE ready
When DTE ready to send data, it asserts Request to
Send (RTS)

1.
2.

3.
4.
5.
Also inhibits receive mode in half duplex
Modem responds when ready by asserting Clear to
send (CLS)
DTE sends data
When data arrives, local modem asserts Receive
Line Signal Detector and delivers data
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Modem Control Signals
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Dial Up Operation (1)
(2) TX
(6) DTE B Asserts DTR
(1) DTR
(7) DCE B asserts DSR
(3) DCE A Dials
(5) Alert DTE B
(4) DCE B detects
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Dial Up Operation (2)
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Dial Up Operation (3)
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SPI Configuration Registers

The SPI configuration registers include
1. A Baud-Rate Register
2. Two Control Registers.
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SPI Baud Rate
The SPI clock frequency and baud rate are controlled by
SPR2, SPR1, SPR0 bits in SP0BR Register.
The SPI clock frequency and data rates are


RSPI = FSCK = (FP)/2 (SPR+1)
Assume P-clock = 8MHz,



If SPR2, SPR1, SPR0 are zero then the SPI data rate is 4Mbps.
If SPR2, SPR1, SPR0 are ones then the SPI data rate is 31.3Kbps
SPR2 SPR1
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SPR0
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SPI Clock Format




A large number of devices in the market today use
synchronous serial communications.
One of the main problems that face engineers is that
many devices have different timing requirements.
To make the SPI compatible with as many devices as
possible, it is designed to be versatile by providing
programmable clock formats.
The clock format is controlled by the CPOL and CPHA
bits in the SP0CR1 register.
CPOL CPHA
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SPI Clock Format




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CPOL  controls the
clock polarity.
The polarity bit
CPOL, determines
the clock edge used
to sample the data.
CPHA  controls the
clock phase.
The phase bit CPHA
determines whether
the first clock edge or
the second clock
edge qualify the data
to be valid.
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Miscellaneous SPI Configurations



SPIE : SPI Interrupt Enable (if 1, then the SPI interrupt
occurs when SPIF or MODF flags are set)
SPE: SPI System Enable (if 1  SPI Enabled)
MSTR: SPI Master/Slave Mode (if 1  Master Mode)
SPIE
SPE
MSTR
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Miscellaneous SPI Configurations
SSOE: Slave Select Output Enable Bit




0 = /SS pin is used for the MODF function (Mode Fault Flag)
1 = /SS function is enabled
LSBF: LSB First Enable Bit (if 1 Data are sent LSB first)
SSOE LSBF
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SPI Status/Data Register


To transfer data to or from a slave device, a program
must make use of the SPI status register, SPOSR, and
the SPI data register, SP0DR.
To send data, the program must test the SPI transfer
complete flag, SPIF, and write the data to the SPI data
register, SP0DR.
SPIF
BIT 7
BIT 0
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