Transcript Simultaneous Photon Counting and Charge Integrating

Simultaneous Photon Counting and
Charge Integrating Readout Electronics
for X-ray Imaging
Hans Krüger, University of Bonn, Germany
SI LAB
Silizium Labor Bonn
University of Bonn: Michael Karagounis, Manuel Koch, Edgar Kraft,
Hans Krüger, Norbert Wermes
University of Mannheim: Peter Fischer, Ivan Peric
Philips Research Laboratories Aachen: Christoph Herrmann,
Augusto Nascetti, Michael Overdick, Walter Rütten
FEE2006, Perugia
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Motivation
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 Photon counting
• limited to count rates < 10 MHz / pixel
• Quantum limited noise statistics
 Charge integration
• High photon flux
• does not reach quantum limited resolution at low photon flux
photon counter
integrator
sim. counting and
integrating (CIX)
# photons
yes
no
yes
total energy
no
yes
yes
low flux
yes
no
yes
high flux
no
yes
yes
spectral
information
no
no
yes
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(mean photon energy)
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Counting and Integrating X-ray Detection (CIX)
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more information
from the same x-ray dosage
Integrator
Photon counter
signal intensity
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Pixel Concept
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Conversion Layer
Total deposited
energy
Integrating Channel

Counting Channel
Preamp
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Mean photon
energy
Number of
absorbed photons
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 Implementation
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Prototype chip CIX 0.1
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chip features:
• AMS 0.35 µm CMOS technology
• area per electronics channel:
100 µm  547 µm
• linear arrangement of 17 cells
(no bump bond pads)
2 test pixels with access to sub-circuits, e.g.
preamplifier analog output
• in-pixel signal generation circuits
(design for testability)
• low noise digital logic
(low-swing differential current steering
logic, DCL)
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Pixel Cell Block Diagram

preamp with continuous reset
replication of feedback current sourced
to the integrator
Charge integration (I to F converter)
-

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Photon counting
-

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comparator output triggers charge
pump (synchronous)
constant charge packet removed from
integrator feedback capacitor Cint
number of pump cycles and
timestamps for first and last cycle
stored
Signal simulation
-
switched capacitor and switched
current charge injection circuits
internal/external dc current source
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Integrator: Charge Packet Counting
UCINT
UCINT
Time320µs
small current
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fclk = 8 MHz
pump cycles = 2
Time = 2560
Imeas [pkts./clk] = 1/2560
= 0,0004
t
Time(1/3)*320µs
larger current
fclk = 8 MHz
pump cycles = 2
Time = 853
Imeas [pkts./clk] = 1/853
Frame=320µs
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t
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= 0,0012
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Feedback Circuit

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3 differential pairs:
• continuous reset of the CSA feedback capacitor
• signal replication to source the integrator
• leakage current compensation
leakage current compensation
feedback
(slow)
(fast)
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Charge injection circuits (chopper)
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• chopper 1+2: switched capacitors (~10 fF), connected to preamplifier input
• current chopper:
switched current source (800 nA max.), connected to preamplifier or integrator input
minimal pulse duration ~30 ns
• leakage current simulation
• up to five load capacitors (~100 fF each) connected to preamplifier input
Chopper 1
current chopper
IntIn
VDDChopper
/IntCurrInjEn
VCal
Leakage
current
simulation
to integrator
Input
capacitance
simulation
to preamplifier
/AmpCurrInjEn
/Str1
CascBias
Chopper 2
ICurrInjN
/Str2
SelLoad0..4
VDDA
ILeakSimN /LeakSimEn
Cinj
/ChInjEn
AGND
AGND
VDDChopper
StrCurr
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Integrator and Charge Pumps
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• switched capacitor charge pump:
dQ = (VDDA - VIntRef) · 240 fF, typical charge packet 1.8 · 106 e- (i.e. 140 60 keV photons or
170 photons at 120 keV tube spectrum)
1.7µA maximal current throughput (at 6 MHz clock rate)
• switched current charge pump
packet size controlled by IPump bias DAC and clock rate
• VIntTh controls charge pump trigger level
/Reset
IPumpP
CurrPump
/CurrPump
current pump
240f
VDDA
ChPumpRes
ChPump
capacitive pump
300f
CompOut
VIntRef
VIntTh
Integrator
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Comparator
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Differential Current Mode Logic
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 Differential pair with constant bias
current Ibias
Ibias
- loads generate low voltage swings by
I to U conversion
in
in
out
out
 An ‘ideal’ load characteristic:
- Vhi level fixed at maximum possible
input voltage (~VDD-Vth –VDsat)
- Vlow level fixed by the voltage swing
required to ‘fully’ switch the current in
the cell (~200 mV)
- plateau at ½ Ibias guarantees equal
rise and fall times
- and all this independent of the
absolute value of Ibias to match given
loads and speed requirements
Load
IU
CML principle (inverter)
Iload
Ibias
½ Ibias
Vlo
P. Fischer, E. Kraft, “Low swing differential logic for mixed signal
applications”, Nucl. Instr. Meth. A 518 (2004) 511-514
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Load
IU
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Vhi
Vload
'ideal' load characteristic
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Implementation of the load circuit
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 Approximation of the ideal load circuit
-
in
NMOS operated as a current source with
adjustable voltage VSS
diode connected NMOS (or pn-diode) to ground
 Vhi increases only little with Ibias
 Differential swing can be adjusted through VSS
measured load characteristic
2,0
Iload [µA]
bias
VSS
GND
Iload
VSS=0V, Bias A
VSS=0V, Bias B
VSS=0.2V, Bias A
VSS=0.2V, Bias B
1,5
Load
IU
½ Ibias
1,0
Vlo
Vhi
Vload
0,5
DAC=15/31
0,0
0,0
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0,1
0,2
Vload [V]
0,3
0,4
0,5
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 Measurements
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Photon Counter Performance
minimum operational
threshold
500 e
equivalent noise charge
180 e + 79 e / 100 fF
maximum count rate
6 (12) MHz with static (dynamic)
leakage current compensation
double pulse resolution
>100 ns
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Integrator Noise Performance
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discretisation limit
Poisson
SNR limit
perfect
12-bit ADC
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Impact of the Feedback Circuit
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DIRECT injection
via feedback
Poisson
SNR limit
 noise performance not optimal but Poisson statistics limits SNR for real
X-ray photon detection (60 keV X-rays, CdTe sensor, 320 µs frame time):
- 100 pA  23 ph, sqrt(23) = 4,8
- 1 nA  226 ph, sqrt(226) = 15
- 10 nA  2260 ph, sqrt(2260) = 48
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Total Dynamic Range
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200 nA
integrator
12 nA
6 MHz max.
overlap region
pulse frequency
66 pA
photon counter
a single pulse
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3 pA
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Reconstruction of the Mean Photon Energy
total energy / photon count
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photon counter
overload
original pulse size
integrator lower limit
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Summary
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 A readout scheme which is capable of simultaneous counting and
integrating absorbed X-ray quanta has been proposed and implemented
 The multi-stage feedback circuit of the pre-amplifier mirrors the signal
current to the integrator and provides leakage current compensation
 A prototype chip has been submitted and tested and showed the feasibility
of the concept
 The simultaneous operation is fully functional though still impaired by
the excess noise of the (not optimized) feedback network
 A new test chip has been submitted and is currently under study
Acknowledgements:
Edgar Kraft for the animated ppt – sildes
References:
• E. Kraft et al., “Counting and Integrating Readout for Direct Conversion X-ray Imaging - Concept,
Realization and First Prototype Measurement”, Proceedings of the IEEE 2005 NSS/MIC
• P. Fischer, E. Kraft, “Low swing differential logic for mixed signal applications”,
Nucl. Instr. Meth. A 518 (2004) 511-514
FEE2006, Perugia
Hans Krüger, University of Bonn
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