Transcript Process Compensated High Speed Ring

Process Compensated High Speed Ring Oscillators
in Sub-Micron CMOS
Xuan Zhang, Mustansir Mukadam, Ishita Mukhopadhyay, and Alyssa Apsel
Cornell University
Ithaca, NY
USA
12/12/2010
CASFEST 2010, Athens, Greece
Outline
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



Introduction
Related Work
Proposed Solution
Measurement Results
Conclusion
Variability in Deep Sub-micron Nodes
90nm
45nm
D2D
15%
18%-28%
WID
3.5%
5.4%-6.6%
Proximity
Effects
10%
2%
WID Spatial
Dependence
High
Low
Major Source
Poly-Si
density
CESL/STI
stress
Line Edge Roughness (LER)
Random Dopant Fluctuation (RDF)
Source: L.T. Pang, et al., JSSC, 2009.
Source: A. Asenov, et al., Async, 2008.
Source: Intel Technology Journal, 2008.
D2D – die-to-die
WID – within die
CESL – contact etch stop layer
STI – shallow trench isolation
Impact on Circuit Design
 Dilemma for mixed-signal design
 Increasing ft and fmax
 Higher density integration
 Better power efficiency
Source: U.Mich, SODA Architecture, Micro, 2007.
 Higher variability
=> yield loss
=> design constraints
Source: A. Nieuwoudt, et al., DAC, 2005.
Why High Speed Oscillators?
 Ubiquitous in Integrated Circuits
 High-speed I/O
 Phase-locked loop
 Low power transceiver
 Wake-up radio
 Uncertain IF architecture
 Super-regenerative
Source: N. Pletcher, et al., JSSC, 2009.
Stability
Area
Power
Phase Noise
Accuracy
Source: J. Bohorquez, et al., JSSC, 2009.
Tuning Range
Frequency Variation in Ring Oscillators
 Highly susceptible to process variation
 Implications to the system
 Critical design constraints
 Over-design
 Sacrifice other specs
Source: H. Masuda, et al., CICC, 2005.
Chip-to-chip variation more than 20%
Source: S. Drago, et al., TCAS-I, 2009.
Outline





Introduction
Related Work
Proposed Solutions
Measurement Results
Conclusion
Test Phase: Trim, Fuse & Calibrate
 Accuracy and Flexibility
 High quality external references
 One-time or programmable
 Cost is Catching Up
 Automatic testing equipment
 Built-in complexity
 Sophisticated testing scheme
Testing time is a cost, need to minimize.
Laser Trim
Poly-Si Fuse
Calibration
Cost
High
Low
High
Overhead
Low
High
High
Reversible?
No
No
Yes
Source: ITRS Road map report, 2001.
Layout Phase: Lithography & Layout
 Resolution Enhancement
 Optical proximity correction
 Off-axis illumination
 Phase-shift mask
Only fixes one source of variation.
 Layout Techniques
 Common-centroid
Only improves local matching.
Design Phase: Redundancy and Global Tuning
 Global Tuning in Processors
 Adaptive body bias (ABB)
 Within-die ABB
 Adaptive VDD
Off-chip crystal oscillator is needed.
Source: J. Tschanz, et al. DAC 2005.
 Redundancy and Re-configurability
 Duplicate ADC stages
 Novel coding in DAC
 Multiple oscillator in PLL
Area and complexity penalty for high precision matching.
Source: D. Daly, et al. JSSC 2009.
Design Phase: Self-Compensated Circuits
Step I:
Write output
function
X  F (C, b , P , T )
Step II:
Calculate
variation
Step III:
Set variation
term to 0
X  f (b , P , T )
X  0
b  f 1 ( P , T )
voltage, current,
transconductance
I=I1+I2: the addition current.
I1, I2: negatively correlated.
I  (1 
2
)I 1   2 (V gs 2  Vth2 )  1 V gs 2
1
To engineer the correlation such that
statistically ΔI1= -ΔI2, Vgs2 is generated by
V gs 2  I 1
1   2 1
 I 1 R
 2 (V gs 2  Vth2 )  1
Step IV:
Implement
in circuits
Design Phase: Feedback Loop
 Negative Feedback in Circuits
 Gain desensitization
Source: B. Razavi, McGraw, 1997.
 Example:
 Amplifier: gain matched to C1/C2 ratio
 PLL: phase matched to reference
Since loop gain is unit-less, input and output share the same unit
Require high precision reference in the same domain.
Existing Low Variation Oscillators
 External Frequency Reference
 PLL regulated local oscillator
 Post-process calibration
 Extract timing from data
Source: C. Chan, JSSC, 2010.
 Fully-Integrated with No External Component
 Novel structure as reference
(eg. thermal-diffusivity, silicon resonator )
 Relaxation oscillator
 low power, low frequency (~KHz)
 Ring Oscillator
Source: S. Kashmiri, JSSC, 2010.
Existing Low Variation Oscillators
 External Frequency Reference
 PLL, calibration, data timing extraction
 Fully-Integrated with No External Component
 Novel device as reference
 Relaxation oscillator
 Ring oscillator
 sensing threshold and tuning Vctrl
Source: K. Sundaresan et al, JSSC 2006.
Approximation only valid for ~MHz.
 constant gm with big capacitor
Power hungry to sustain high gm for high frequency
How to design a low-power, low-cost, low-variation on-chip oscillator at GHz?
Outline
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



Introduction
Related Work
Proposed Solutions
Measurement Results
Conclusion
Process Compensation Loop
Perform frequency  voltage conversion
(current charging a capacitor)
 Basic System Concept
=> Convert frequency to a DC value
=> Compare it to a DC reference
=> Generate the correction to Vctrl
Eliminate off-chip frequency reference.
Perform the comparison at lower rate.
Transform
error signal  correction voltage
Comparator-Based Loop
Functional model for each block
Comparator
Frequency accuracy:
f 
 0
 f osc
2

   0T

 Tosc
2

 
   0 I
 I REF

2
  C
   0
  C FS
2

 

2
2
 REF
  CP
,off 
V 
2
 UP
 DN
2
ACP
Gm2
2
0
REF
VREF>>σREF, σCP,off, ACP>>1
Charge Pump
Static oscillation period:
Tosc 
C FS
NI REF

I  I DN
VREF  VCP ,off  UP
2 ACP Gm




Frequency Sensor
 Process-Invariant Block
 Low variation current source
 Charge sharing between big cap
Sample
Share
Reset
VP 
I REF NTOSC
C1
VFS
n
  C


2
1  
 I NT

  C1  C2   REF OSC


C1
Comparator, VCO and Charge Pump
 Comparator
 diff-pair
 large matching
input
 Charge pump
 VCO
 IUP=IDN=150µA
 3-stage current-starved
ring oscillator
 IUP and IDN matched
when VCP,out=VDD/2
 780MHz~5.6GHz
Loop Dynamic and Stability
 Two Phases in Loop Dynamic
 Bang-bang region
 large initial freq offset
 binary comparator output
 Near locking
 continuous-time approximation
Freq
acquisition
with different
initial offsets
in bang-bang
region
Root Locus (3 poles)
Step Response
Switched Capacitor-Based Loop
To improve stability, the correction should be proportional to the error signal.
Thus ideally, we want
I REF NTosc (n)  VREF C1
Vctrl (n  1)  Vctrl (n) 
This can be realized by switched capacitors.
(a) initialization
(b) comparison
C2
error represented by charge difference
(c) correction
Frequency Accuracy
If the finite gain and offset of the opamp
are considered, the update equation needs
to be modified:
Vx (n  1)  Vx (n)
V C  I REF NTosc (n)
C2 ( A  1)
 REF 1
C1  C2 ( A  1)
C1  C2 ( A  1)
Static oscillation period:

Tosc

Frequency accuracy:
f
 0
 f osc
2


   0T

 Tosc
2

 

  K2 '
 
 '  C0 
2
2
2
 KVCO C1     C    V   off
2
2
 C0 
0
0
I REF
VREF
 1 
C12
  2 '2
A KVCO
2
I




(VREF  Voffset )C1

C1
N  I REF 
'
A.KVCO




Again, variations in IREF and C1 dominate.
Outline





Introduction
Related Work
Proposed Solutions
Measurement Results
Conclusion
Calibrated with External Current Source
 Single-point current calibration
 baseline case


current-biased RO
8.7% variation
 process compensated


2.6% variation due
mostly to cap tolerance
3.3x improvement
Post-process calibration
process can be simplified
Fully On-Chip with Addition-Based Current Source
 Full integrated on-chip
 baseline case


current-starved RO
with fixed Vctrl
17.7% variation
 process compensated



freq correlated with the
addition-based current
4.6% variation
3.8x improvement
Frequency accuracy can be
improved without
external component.
Multiple Wafer-Run Results
Switched Cap. Based Loop
Multiple wafer-runs have been taped out in 90nm CMOS.
Consistent improvement is observed from more than 200 chips.
Temperature and Supply Voltage Sensitivity
To the first order, fosc is proportional to


I REF
VREF C
C is usually constant with T and VDD
IREF is provided by the addition-based current source
 90ppm/oC temperature sensitivity
 linear with VDD, if biased generated from a VDD divider.
Measured (168ppm/oC)
Simulated (IREF and fosc vs VDD)
Temperature and Supply Voltage Sensitivity
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Designed for above 2GHz range
Area<0.01mm2
Power: 1.95mW
Verified by chips from 2 lots
Taped out in 90nm CMOS
Conclusion
 Investigated the validity of a process compensation scheme based on feedback
loop that uses DC blocks (current source) as low variation “ruler-on-chip” to
calibrate high speed oscillators.
 Demonstrated two implementations of the proposed process compensation loop
in: 1) a comparator-based system and 2) a switched capacitor-based system, and
provided detailed discussion on their frequency accuracy and loop dynamics.
 Presented comprehensive measurement results showing: 1) with single point
current calibration, better than 2.6% frequency accuracy can be achieved; 2)
without calibration and off-chip component, 4.6% frequency accuracy can be
achieved– a 3.8x improvement over the baseline case.
 Similar reduced sensitivity to temperature and supply voltage has been
simultaneously accomplished.
Reference
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Xuan (Silvia) Zhang
Thank You.
Mustansir Mukadam
Ishita Mukhopadhyay