Transcript PPT - The University of Toledo - Engineering Technology Department

Antifuse-Based FPGAs:
Actel
CSET 4650
Field Programmable Logic Devices
Dan Solarek
Antifuse FPGAs
One-time programmable devices
Primary vendors
Actel
QuickLogic
No longer producing antifuse devices
Xilinx
Cypress
Focus on Actel today
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New Architecture
Actel FPGAs have evolved
from the channeled logic
array architecture (e.g.,
used in ACT series) to the
“Sea-of-Modules”
architecture
Made possible because
antifuses and wires can be
fabricated above the chip
“floor” in the third
dimension
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Antifuse Switch
Antifuses are originally open circuits that take on low resistance only
when programmed.
Antifuses are manufactured using modified CMOS technology.
Metal 3 (parallel to page)
Metal-to-Metal Antifuse
Metal 2 (into page)
Via
Metal 1
contact
Silicon
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Antifuse Switch
Here is a three-dimensional
representation of the same
type of routing resources
Some contacts shown are
permanent, not switched
Programmable antifuses are
shown in green
Routing elements of this
type allow more density of
logic elements in silicon
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ONO Antifuse: Actel
The figure below illustrates Actel’s PLICE (programmable
logic interconnect circuit element) antifuse structure.
The antifuse, positioned between two interconnect wires,
consists of three sandwiched layers:
conductors at top and bottom
an insulator in the middle
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ONO Antifuse: Actel
Unprogrammed, the insulator isolates the top and bottom
layers; programmed, the insulator becomes a low-resistance
link.
PLICE uses polysilicon and n+ diffusion as conductors and a
custom-developed compound, ONO (oxide-nitride-oxide), as
an insulator.
Other antifuses rely on metal for conductors, with amorphous
silicon as the middle layer.
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ONO Antifuse: Actel
An antifuse is the opposite of a fuse.
It is an open circuit until a current is forced through it (about 5 mA).
The current melts a thin insulating layer to form a thin permanent and
resistive link.
(a) A cross section. (b) A simplified drawing. The ONO (oxide–nitride–oxide) dielectric is
less than 10 nm thick, so this diagram is not to scale. (c) From above, an antifuse is
approximately the same size as a contact.
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Antifuse Advantages
Highest density
a simple cross point
10X the density of SRAM
Lowest switch resistance
~25 Ohms
Very low capacitance
~1 fF per node
approaching the metal line
capacitance
Nearly impossible to
reverse engineer
Radiation hard
Live within 1 millisecond
of the power supply
reaching spec voltage
Software is easy to place
and route
non-volatile
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Antifuse Disadvantages
Requires programmer
Requires a socket
a problem for devices with
more than 200 pins
Those who design by test
will throw out a lot of parts
Requires one or two
transistors per wire for
programming
ONO antifuses require only
about 5mA for programming
~ 10mA for Metal antifuses
Some antifuse defects not
testable until programming
hence only 98% to 99 %
programming yield
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FPGA Qualitative Comparison
SRAM
Antifuse
Flash
EPROM
Speed
Worst
Best
Worst
Medium
Power
Varies
Near Best
Best
Worst
Density
Medium
Second
Best
Worst
Worst
Best
Medium
Medium
Routing Cell size
1
1/10
1/7
PLD
Reprogrammable
Yes
No
Yes
Yes
Radiation
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Actel’s Current Antifuse Devices
Axcelerator
High-speed antifuse FPGAs with gate densities of up to 2 million
equivalent gates
SX-A / SX
Antifuse devices 8k to 72k gates
eX
Antifuse devices 3k to 12k gates
MX
Antifuse devices 3k to 54k gates
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Actel’s Legacy Devices
Integrator Series FPGAs:
1200XL and 3200DX Families v3.0
Accelerator Series FPGAs
Devices being phased out
or already discontinued.
ACT 3 Family (-3 speed grade only)
ACT 2 Family FPGAs v4.0.1
ACT 1 Series FPGAs
Speed Grade
Std = Standard Speed
–1 = Approximately 15% faster than Standard
–2 = Approximately 25% faster than Standard
–3 = Approximately 35% faster than Standard
–P = Approximately 30% faster than Standard
–F = Approximately 40% slower than Standard
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Actel MX Family
low power consumption
5.0V, 3.3V and mixed voltage systems compatible
design security
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Actel MX Family
Naming convention
Six devices in the MX
family, vary in number
of equivalent gates
Five speed grades
A variety of package
options and operating
temperature ranges
Same convention used
for all Actel FPGAs
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Actel MX Family
MX 40M and 42M devices
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40MX Logic Module
Same as ACT 1 logic element
eight-input, one-output logic
circuit (702 possibilities)
can implement the four basic
logic functions (NAND, AND,
OR and NOR) in gates of two,
three, or four inputs
can also implement a variety
of D latches, exclusivity
functions, AND-ORs and ORANDs
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42MX C-Module Implementation
42MX devices contain
three types of logic
modules:
combinatorial (C-modules)
sequential (S-modules)
decode (D-modules)
figure at right illustrates
the combinatorial logic
module
766 possibilities
Actel’s name for combinational logic
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42MX S-Module Implementation
S-module implements the same
combinatorial logic function as the
C-module while adding a sequential
element.
Sequential element can be
configured as either a D-flip-flop or
a transparent latch.
S-module register can be bypassed
so that it implements purely
combinatorial (combinational) logic
functions.
S-Module
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42MX S-Module Implementation
A closer look at the S-Module configurations
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A42MX24 and A42MX36 D-Module
Implementation
D-modules are arranged
around the periphery of the
device.
D-modules contain widedecode circuitry, providing
a fast, wide-input AND
function similar to that
found in CPLD
architectures
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A42MX36 Dual-Port SRAM Block
The SRAM modules are
arranged in 256-bit blocks
that can be configured as
32x8 or 64x4.
SRAM modules can be
cascaded together to form
memory spaces of userdefinable width and depth.
A42MX36 SRAM modules
contain independent read
and write ports.
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From Before: Actel’s ACT Series
Based on channeled gate
array architecture
Segmented routing tracks
Interconnect and logic
elements in same plane
Each logic element (labelled
‘L’) is a combination of
multiplexers which can be
configured as a multi-input
gate
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MX Routing Structure
MX architecture uses vertical and
horizontal routing tracks to
interconnect the logic and I/O
modules.
Routing tracks are metal
interconnects that may be continuous
or split into segments.
Varying segment lengths allow the
interconnect of over 90% of design
tracks only two antifuse connections.
Segments can be joined together at
the ends using antifuses to increase
their lengths up to the full length of
the track.
All interconnects can be
accomplished with a maximum of
four antifuses.
L L L L L L L L
L L L L L L L L
L L L L L L L L
Actel’s Channeled Routing
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Horizontal Routing
Horizontal routing tracks span the whole row length
or are divided into multiple segments and are located
in between the rows of modules.
Any segment that spans more than one-third of the
row length is considered a long horizontal segment.
Within horizontal routing, dedicated routing tracks
are used for global clock networks and for power
and ground tie-off tracks.
Non-dedicated tracks are used for signal nets.
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Vertical Routing
Another set of routing tracks run vertically.
There are three types of vertical tracks:
input, output, and long
Long tracks span the column length of the module,
and can be divided into multiple segments
Each segment in an input track is dedicated to the
input of a particular module
Each segment in an output track is dedicated to the
output of a particular module
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Vertical Routing (continued)
Long segments are uncommitted and can be
assigned during routing
Each output segment spans four channels
two above and two below the logic module
except near the top and bottom of the array, where edge
effects occur
Long vertical tracks contain either one or two
segments
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Antifuse Structures
An antifuse is a "normally open" structure
the opposite of a “normally closed” fuse
The use of antifuses to implement a programmable
logic device results in
highly testable structures
efficient programming algorithms
There are no pre-existing connections
temporary connections can be made using pass transistors
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Antifuse Structures (continued)
These temporary connections can isolate
individual antifuses to be programmed
individual circuit structures to be tested
can be done before and after programming
For example
all metal tracks can be tested for continuity and shorts
between adjacent tracks
the functionality of all logic modules can be verified
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From Before: Actel ACT Series I/O Logic
Simple tristate buffers
Allowed pins to be used as
an input or an output, or
both
ACT 1 I/O Module
ACT 2 I/O Module
ACT 3 I/O Module
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Actel MX Family
42MX devices feature
Multiplex I/Os and support
5.0V, 3.3V, and mixed
3.3V/5.0V operations
provide the interface between
the device pins and the logic
array
modules contain tristate
buffers, with input and output
latches that can be configured
for input, output, or
bidirectional operation.
42MX I/O Module
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Actel MX Family
A42MX24 and A42MX36
devices also offer selectable
PCI output drives, enabling
100% compliance with version
2.1 of the PCI specification
chip-wide PCI fuse
When the PCI fuse is not
programmed, the output drive
is standard.
PCI Output Structure of
A42MX24 and
A42MX36 Devices
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Actel eX Family
Low power consumption
Extremely small chip-scale
packages
Design security
Nonvolatile single chip
Up to 100% resource
utilization with 100% pin
locking
2.5V, 3.3V, and 5.0V Mixed
Voltage Operation with
5.0V Input Tolerance and
5.0V Drive Strength
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Actel eX Family
eX naming convention
three devices in the eX
family, vary in number
of equivalent gates and
flip-flops
three speed grades
a variety of package
options and operating
temperature ranges
same convention used
for all Actel FPGAs
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Actel eX Family
Device selection
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Actel eX Family
The eX family architecture uses a “sea-of-modules” structure
where the entire floor of the device is covered with a grid of
logic modules with virtually no chip area lost to interconnect
elements or routing.
Interconnection among these logic modules is achieved using
metal-to-metal programmable antifuse interconnect elements.
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Actel eX Family
eX family provides two types
of logic modules
the register cell (R-Cell)
the combinatorial (combinational)
cell (C-Cell)
C-Cell is shown at right
similar to ACT logic cell of the
same name
inverter input (DB) added
allows ~4000 possible
combinational functions to be
implemented
C-Cell
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eX R-Cell
The R-Cell contains a flip-flop
featuring asynchronous clear,
asynchronous preset, and clock enable
(using the S0 and S1 lines) control
signals.
The R-Cell registers feature
programmable clock polarity
selectable on a register-by-register
basis.
This provides additional flexibility
while allowing mapping of
synthesized functions into the eX
FPGA.
The clock source for the R-Cell can be
chosen from either the hard-wired
clock or the routed clock.
R-Cell
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Actel eX Family
C-cell and R-cell logic modules are arranged into horizontal banks
called Clusters, each of which contains two C-cells and one R-cell in a
C-R-C configuration.
Clusters are further
organized into
modules called
SuperClusters.
Each SuperCluster
is a two-wide
grouping of
Clusters.
Cluster Organization
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Actel eX Family: Routing Resources
Clusters and SuperClusters can be connected through the use of two
local routing resources called FastConnect and DirectConnect.
This routing architecture
reduces the number of
antifuses required to
complete a circuit.
DirectConnect is a
horizontal routing
resource that provides
connections from a C-cell
to its neighboring Rcell in
a given SuperCluster.
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DirectConnect and FastConnect for SuperClusters
Actel eX Family: Routing Resources
DirectConnect uses a hardwired signal path
requiring no programmable interconnection.
FastConnect enables horizontal routing between any
two logic modules within a given SuperCluster and
vertical routing with the SuperCluster immediately
below it.
Only one programmable connection is used in a
FastConnect path.
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Actel eX Family
eX devices have a variety of
I/O features, such as PCI
compliance, programmable
input threshold voltage,
configurable output slew rate,
and selectable output state
during power-up
support for both hot-swapping
and cold-sparing
mixed I/O standards can be
set for individual pins
only allowed with standards that
use the same supply voltage
Simplified I/O Circuitry
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Actel eX Family
Each I/O on an eX device
can be configured as an
input, an output, a tristate
output, or a bidirectional
pin
I/O cells in eX devices do
not contain embedded
latches or flip-flops and can
be inferred directly from
HDL code.
I/O Features
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Actel SX-A and SX Family
12,000 to 108,000 usable system gates
3.7ns clock-to-output (pin-to-pin)
350MHz internal clock frequency
66MHz, 64-bit 3.3V/5.0V PCI
performance
Hot swappable I/Os (SX-A)
Able to run at OC3 to OC192 data rates
2.5V, 3.3V, and 5.0V mixed voltage
support
100% resource utilization with 100%
pin locking
Low power consumption (less than 1W
@ 200MHz)
Complete BST/JTAG support
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Actel SX-A and SX Family
54SX Family
FPGAs
available in four
speed grades
six package options
four component
densities
four operating
temperature ranges
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54SX32A
Actel SX-A and SX Family
As with the eX Family, the SX-A and SX Families use
Actel’s “Sea of Modules” architecture
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Actel SX-A and SX Family
the C-cell implements a range
of combinatorial functions up
to 5-inputs
inclusion of the DB input and
its associated inverter function
dramatically increases the
number of combinatorial
functions that can be
implemented in a single
module from 800 options in
previous architectures to more
than 4,000 in the SX
architecture
C-Cell
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Actel SX-A and SX Family
the R-cell contains a flipflop featuring
asynchronous clear
asynchronous preset
clock enable (using the S0
and S1 lines) control signals
the R-cell registers feature
programmable clock
polarity selectable on a
register-by-register basis.
R-Cell
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Actel SX-A and SX Family
C-cell and R-cell logic modules
are arranged in horizontal banks
called Clusters
two types of Clusters:
Type 1 contains two C-cells
and one R-cell
Type 2 contains one C-cell and
two R-cells
SuperCluster 1 is a two-wide
grouping of Type 1 clusters.
SuperCluster 2 is a two-wide
group containing one Type 1
cluster and one Type 2 cluster
Cluster Organization
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Actel SX-A and SX Family
Clusters and SuperClusters can be
connected through the use of two
local routing resources called
FastConnect and DirectConnect
This routing architecture reduces the
number of antifuses required to
complete a circuit
DirectConnect is a horizontal routing
resource that provides connections
from a C-cell to its neighboring R-cell
in a given SuperCluster
DirectConnect and FastConnect
for Type 1 SuperClusters
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Actel SX-A and SX Family
DirectConnect uses a hardwired signal path requiring no
programmable interconnection
to achieve its fast signal
propagation time of less than
0.1 ns
FastConnect enables
horizontal routing between
any two logic modules in a
given SuperCluster and
vertical routing with the
SuperCluster immediately
below it
Only one programmable
connection is used in a
FastConnect path, delivering
maximum pin-to-pin
propagation of 0.4 ns
0.4 ns
DirectConnect and FastConnect
for Type 2 SuperClusters
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Actel SX-A and SX Family
Each I/O module on an SX device can be configured as
an input
an output
a tristate output
a bidirectional pin
Even without the inclusion of dedicated I/O registers, these I/O
modules, in combination with array registers, can achieve
clock-to-out (pad-to-pad) timing as fast as 3.7 ns.
I/O cells that have embedded latches and flip-flops require
instantiation in HDL code; this is a design complication not
encountered in SX FPGAs.
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Actel SX-A and SX Family
the SX family locates the
routing interconnect resources
between the Metal 2 and Metal
3 layers
this eliminates the channels of
routing and interconnect
resources between logic
modules
metal-to-metal programmable
antifuse interconnect elements,
which are embedded between
the M2 and M3 layers
SX Family Interconnect Elements
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Actel SX-A and SX Family
SX-A interconnect resources
are located between the top
two metal layers
A54SX72A has four layers of
metal with the antifuse
between Metal 3 and Metal 4
A54SX08A, A54SX16A and
A54SX32A have three layers
of metal with antifuse
between Metal 2 and Metal 3
Same as SX
SX-A Family Interconnect Elements
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