Transcript L-3: Embedded Processors Short Course, Part A

Computer Architecture: Intro
Beginnings
J. Schmalzel
S. Mandayam
Course
 Introduction
 Overview
 Content launch: Module 1
Structure & Conduct of the
Course
 Discussion v. Lecturing
 Interaction: Question/Comment Ticket
 Team-learning
 In-class labs
 Out-of-class labs, readings, problems
Introduction
 Instructors: J. Schmalzel, S. Mandayam
 Course
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Digital Foundations
Introduction to Embedded Processors
The Embedded Development Environment
Interfacing to the Physical World
Hardware and Software Trade-Offs
Course Goal
 Goal: Impart knowledge of computer
architecture to support informed decisions
about the hardware, software, and the
hardware/software trade-offs that underlie
the computing paradigm.
Objectives, 1
 Describe major functional elements of CISC, RISC
architectures
 Perform detailed analysis and synthesis of
combinatorial and sequential subsystems using
schematic and/or behavioral design capture w/ sim
 Describe principles and applications of the three
basic computing elements: CPU, MEM, I/O
 Use an embedded system that includes diverse
architectural features
Objectives, 2
 Apply analytic and simulation techniques to predict
and verify performance metrics
 Design an example architecture using SOTA tools
 Identify opportunities for hardware and software
trade-offs
 (Insert your objectives here…)
(
…and here)
Digital Foundations
 The basic model of a computer system:
CPU
MEM
I/O
Central Processing Unit (CPU)
 Controls
 Executes
 Computes (Fixed- and/or FloatingPoint)
Memory
 Program store
 Data storage
 High-speedLow-speed
 Volatile, Non-volatile
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RAM, ROM, FLASH (EEPROM)
 FastSlow
Input/Output (I/O)
 Communication between CPU and
outside world
 FastSlow
 Standardized (e.g., IEEE 802.11b)
 Parallel (IEEE 1184)Serial (USB
2.0)
Hierarchical View of EP and
Digital Systems
CPU
MEM
Computer
Architecture
I/O
Operating
System
HLLs
State
Machines
Interface
Method
MSI
Functions
Design
Techniques
Gates
Boolean
Algebra
Number Systems
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Binary
Hexadecimal
Octal
For an n-bit binary number:
Base notation. For a k-bit binary number with n-bits to the left of
the radix point and m-bits to the right of the radix point.
bn 1 2 n 1  bn  2 2 n  2  ...  b2 2 2  b1 21  b0 20.b1 2 1  b 2 2 2  b3 2 3  ...  b m 2  m
For example, 1101001.101 = ______________10
= (64 + 32 + 8 + 1) . (0.5 + 0.125)
= 105.625
Similarly, for hex:
hn 116 n 1  ...  h0160.h116 1  ...
Conversions
11111111  ____________(10)
(Fast way: 100000000 -1 = 255)
10101010.01  _____________ (10)
(AA.416 = 10*16 + 10 + .25 = 170.25)
AB6C.D 
_________________________ (2)
 ___________(10)
(1010101101101100.1101; 10*4096 + 11*256 +
6*16 + 12 + 13/16 = 43,884.8125)
Coding
Binary system must be used to accomplish
many functions such as arithmetic and data
transmission. A code defines the mapping
between binary digits and the intended
application.
Example Codes
 Gray code: Only one bit change
between adjacent codes
(000010110100
101111011001000…)
 Binary-Coded Decimal (BCD): Direct
(but inefficient) coding of decimal
numbers using 4 bits
2’s Complement
Need: A method to represent negative numbers. Can
use a sign bit + magnitude; e.g., +5: 0 101, -5: 1 101,
but there are better codes. The 2’s Complement is one.
1’s Complement: Complement each bit.
1’s Complement of 11011 is 00100
2’s complement: 1’s complement + 1
Example: Find 2’s complement of 1001100. 
_______________ (0110100.)
To check, sum of the positive and negative codes
should sum to zero (ignore overflow out of msb).
(“By inspection” trick: Working from right to left, write down all
zeros until the first 1. Write it down, too, then complement every
bit after that.)
Boolean Algebra
 True/False
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High/Low
On/Off
+5 Vdc / 0 Vdc (+3.3 Vdc / 0 Vdc)
 Notation
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Variable by itself is assumed “true”
Variable with a symbol denotes
complementation: ¯ ~ * /
Boolean Identities
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X0=0
X1=X
XX=X
XX*=0
X+0=X
X+1=1
X+X=X
X+X*=1
X**=X
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Commutative Laws:
X+Y=Y+X
XY=YX
Associative Laws:
X+(Y+Z)=(X+Y)+Z
X(YZ)=(XY)Z
Distributive Laws:
X(Y+Z)=XY+XZ
DeMorgan’s Theorems:
(XY)*=X*+Y*
(X+Y)*=X* Y*
Gates (p. 63 M&K)
AND ( ^ • & C: & )
OR (  + C: | )
NOT {Inverter} ( ¯ ~ * / C: ~ )
XOR (  C:  )
NAND
NOR
XNOR
Combinatorial Design Process
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Problem statement
Truth table and describing Boolean Algebra
Simplification
Implementation
Verification
Design Examples
 Full Adder (Step 1: Design a device that
performs binary addition, including carry
input.)
A
B
Ci
S
FA
Co
Full Adder Truth Table (Step 2)
Ci A B
S Co
0
0
0
0
0
1
0
1
0
0 0
1 0
1 0
0
1
1
0
1
0
0 1
1 0
1
0
1
0 1
1
1
1
1
0
1
0 1
1 1
Sum-of-Product Boolean
expressions for S and Co:
S = Ci*A*B + Ci*AB* +
CiA*B* + CiAB
Co = Ci*AB + CiA*B +
CiAB* + CiAB
Graphical Simplification (Step 3)
Co
Ci
0
1
00
0
0
01
0
1
11
1
1
10
0
1
AB
Co = AB + ACi + BCi
BCi
AB
ACi
A Karnaugh-Map organizes
truth table entries as a gray
code--only one variable
changes between adjacent
cells. This lets you use the
identities X+X*=1 and
X*1=X to simplify by
inspection. For example, the
AB subcube: ABCi* + ABCi
= AB(Ci*+Ci) = AB(1) = AB
Other Simplification Methods
 Quine-McCluskey algorithm
“Espresso”
http://www-cad.eecs.berkeley.edu:80/Software/software.html
http://cse.bellarmine.edu/espresso (C. Staley; Find it on download.com)
Espresso Demo
Simplify So and Co for FA
Implementation (Step 3)
Translate the simplified BA to a network of gates:
Ci
A
&
Ci
B
&
A
B
&
+
Co
Verification (Step 4)
Verify the proper behavior of the design. Use
simulation techniques to present test vectors and
compare responses to predictions.
Exhaustive
v.
Statistical (Monte Carlo)
Combinatorial Function Blocks
 Decoders
 Multiplexers
Digital Foundations, cont.
 The basic model of a computer system:
CPU
MEM
I/O
Real Gates
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Logic levels are voltage levels
Finite current drive
Timing diagrams
Finite switching speed
Propagation delays
Noise
Logic Levels are Voltage Levels
High
Vdd
VOHtyp
VOHmin
VIHmin
VILmax
Low
Vss
VOLmax
VOLtyp
Finite Current Levels
The electrical circuit model for a digital output (or input)
includes a series impedance. This helps explain why a gate
can’t source/sink unlimited amounts of current (mA v. A).
RS
VOH/VOL
+
VOH’/VOL’
Finite Switching Speeds
Example: Switching speed of an inverter. A timing
diagram shows behavior as it develops with time.
Input (Ideal)
Output
tr
tf
Finite Propagation Delays
Example: Switching speed of an inverter.
Input (Ideal)
Output
tPD
LH
tPD
HL
Noise
How well logic is able to reject noise is described
by its Noise Immunity. The Noise Margin (NM)
is the predicted ability of a device to handle noise
on its inputs and still reliably determine the
correct logic levels.
NML = VOLmax - VILmax
NMH = VOHmin - VIHmin
Logic Levels/Voltage Levels for
@IOH =
74HC138 w/ VCC=5 Vdc
-20A
High
Low
Vdd
Vss
VOHtyp
VOHmin
4.999
VIHmin
3.5 V (0.7*5.0)
VILmax
1.5 V (0.3*5.0)
VOLmax
VOLtyp
0.1 V (0.0+0.1)
@IOL =
0.001
+20A
4.9 V (5.0-0.1)
Variation in VOH and VOL
IOH
Rs
Ideal VOH
or VOL
VOH or
VOL
+
IOL
What is a typical Rs?
This is reference
direction--that’s why IOH
is negative.
Calculation of Rs at IOL of 4 mA
IOH
Rs
Ideal VOH
or VOL
VOH or
VOL
+
IOL
This is reference
direction--that’s why IOH
is negative.
Use 6 Vdc values: 0.26V/.004A =
65 
Propagation delay (6 Vdc)
 From A, B, or C to any Y output: Max 38 ns
 From Enable to any Y output: Max 33 ns
Questions, Comments, Discussion