Transcript lecture08

Building Larger Circuits
Today:
• First Hour: Combinational Building Blocks
– Section 4.1 of Katz’s Textbook
– In-class Activity #1
• Second Hour: Tri-state and Open
Collector Gates, ROMs.
• Section 4.2 of Katz’s Textbook
– In-class Activity #2
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Recap:
• To simplify large Boolean functions, we use logic
minimization software (espresso)
• We can use multi-level minimization when speed
is not a problem.
• Use Programmable Logic Arrays to implement
large circuits in an automated manner.
Today:
We’ll learn about another tool for building large circuits:
higher-level building blocks (modules).
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Building Blocks
A0
Sa
A1
B0
MUX
B1
Sb
MUX
The Idea:
Assemble your system using
generic “building blocks.”
B
A
Examples:
Sum
PLA
Adder,
Multiplexor,
De-multiplexor,
Ss
DEMUX
Decoder,
Encoder
S0
S1
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A 2:1 Multiplexor
I0
I1
2:1
MUX
Z
A
• Terminology
– I0 and I1 are input lines
– Z is the output line
– A is the control signal
• Truth Table
A
Z
Boolean Function:
Z = A' I0 + A I1
0
I0
1
I1
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Expanded Truth Table
I1
I0
A
Z
0
0
0
0
0
0
1
0
A
Z
0
I0
0
1
0
1
1
I1
0
1
1
0
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
1
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Larger MUXes
I0
I1
2:1
MUX
Z
I0
I1
I2
I3
A
I0
I1
I2
I3
8:1
MUX
I4
I5
I6
4:1
MUX
Z
I7
A
A
Z
B
C
B
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Cascading MUXes
I0
I1
I2
I3
0 4:1
1 MUX
2
3S S
1
0
I4
I5
I6
I7
0 4:1
1 MUX
2
3S S
1
0
B
C
8:1
MUX
0 2:1
MUX
1 S
A
Z
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Implementing Logic with MUX
• 2n-1 :1 multiplexor can implement any Boolean
function of n variables
• needs n-1 control variables; the remaining variable is
used as a data input to the multiplexor
• Example:
F(A,B,C) = m0 + m2 + m6 + m7
= A' B' C' + A' B C' + A B C' + A B C
= A' B' (C') + A' B (C') + A B' (0) + A B (1)
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Example
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F
1
0
1
0
0
0
1
1
C
1
0
1
0
0
0
1
1
0
1
2
3
4
5
6
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S2 S1 S0
C
0
1
A
C
C
0
1
F
8:1
MUX
0
1
2
3
B
C
4:1
MUX
S1
S0
A
B
F
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De-multiplexors (DMUX)
Opposite of MUX, also called Decoders
• Decoder: single data input, n control inputs, 2n
outputs
• control inputs (called selects S) represent binary
index of output to which the input is connected
• data input usually called "enable" (G)
• Usually Enable = G = 1
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2:4 DMUX
Enable
Output0
Output1
Output2
Output3
Select0
Select1
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DMUX as a Logic Block
Enable
3:8
DMUX
(decoder)
S2
S1
A
B
S0
0
1
2
3
4
5
6
7
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC
C
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Example
Implement the following 4-input, 3-output Boolean
function using a decoder (DMUX):
F1 = A B C D + A B C D + A B C D
F2 = A B C D + A B C
F3 = (A + B + C + D)
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0
1
2
3
4
5
6
Enb = 1
4:16
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decoder
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9
10
11
12
13
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S3 S2 S1 S0 15
ABCD
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
F1
F1  A B C D  A B C D  A B C D
F2
F3
A B C D
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Do Activity #1 Now
Get to know MUX and DMUX building blocks
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New Kinds of Gates,
Read-only Memory
• New Kinds of Gates, “wired logic”:
– 3-state output gates
– Open-collector gates
– Build a MUX easily with these new gates.
• Read-only Memory (ROM)
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3-State Gates
A
B
OE
“output enable”
Truth Table
Three possible outputs: 0, 1, or Z
Z means output disconnected
Z does not reduce to 1 or 0
Equivalent Circuit
OE
0
1
1
A
A
X
0
1
B
Z
1
0
B
OE
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What’s the Big Idea?
Allows the output of more than one gate to be
connected to the same wire
- “wired logic”
Especially useful for allowing building blocks to
exchange data over shared wires - buses
Device 1
Device 2
Bus
Device 3
Works only as long as only one gate has its output
enabled at the same time
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Multiplexer using 3-State Logic
Non-inverting Buffers
Input0
F
OE
Input1
When InputSelect = 1,
Input1 is connected to F
When InputSelect = 0,
Input0 is connected to F
OE
This is a 2:1 Mux
3-state Buffer
InputSelect
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Open Collector Gates
Another way to connect multiple gates to the same output wire
The output of an open collector gate is like a switch connected to ground
output for logic “1”
I.C.
output for logic “0”
I.C.
Note: If you put a logic probe on an unconnected opencollector pin, it will indicate a logic 0 or nothing.
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Pull-up Resistors
+5V
+5V
Y=0
Y=1
I.C.
I.C.
Resistors: 1 - 10 k typical
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Two Gates and a Resistor
+5V
Y
Y becomes 0 when any one switch is closed
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Wired Logic
+5V
A
B
C
D
Output
Special symbol on
OC gates: output
bar
If A and B are 1, Output is actively pulled low
If C and D are 1, Output is actively pulled low
If one gate is low and the other high, then low wins
If both gates are 1, the Output floats. Pull it high with a
resistor
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So What’s the Big Idea??
+5V
A
B
Output
Output = Wired
(A B + CLogic
D)'
C
D
!!
(A Output(A,B,C,D)?
B)' (C D)'
What= is
= (A' + B')(C' +D')
Click
= A' C' for
+ A' answer
D' + B' C' +B' D'
If A and B are 1, Output is actively pulled low
If C and D are 1, Output is actively pulled low
If one gate is low and the other high, then low wins
If both gates are 1, the Output is pulled up to logic 1.
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Another Practical Issue
Useful for lighting Light Emitting Diodes (LEDs)
+5V
What happens to the LED
when X = 1?
R
No current = OFF
I.C.
X
When X = 0?
Current = ON
Click for the answer
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Read-Only Memories
Sort of like a PLA
structure with a
fully decoded
AND array!
Memory Array
Decoder
n address
lines
2n word
lines
n
2 words by
mbits
m output
lines
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Applications of ROMs
Store data in a non-volatile manner
Like PLA’s, you can buy programmable ROMs
(PROMs)
Implement combinational functions
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ROM vs. PLA
combinational functions
ROM advantageous when
• design time is short (no need to minimize output functions)
• most input combinations are needed (e.g., code converters)
• little sharing of product terms among output functions
Downside:
• size doubles for each additional input
• can't use don't cares
PLA advantageous when
• design tool like espresso is available
• there are relatively few unique minterm combinations
• many shared minterms among the output functions
Downside: constrained fan-ins on OR arrays
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ROM Example
ADDRESS
LINES
2764
VPP
PGM
A12
A11
A10 O7
A9
O6
A8
O5
A7
O4
A6
O3
A5
O2
A4
O1
A3
O0
A2
A1
A0
CS
OE
CHIP SELECT
OUTPUT ENABLE
DATA
LINES
(tri-state)
Questions:
• How many words?
213 = 8K = 8 192
• How many bits in each word?
8
• How many bits overall?
216 = 64K = 65 536
• Click for answer
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Choices, choices ...
You can implement logic functions many ways:
Discrete gates
AND/OR
NAND/NAND
PLAs or PALs
Muxes
Demuxes (decoders)
ROMs
Existence of alternatives  no clear winner
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Do Activity #2 Now
Due: End of Class Today
RETAIN THE LAST PAGE (#3)!!
For Next Class:
• Bring Randy Katz Textbook, & TTL Data Book
• Required Reading:
– Sec 5.1 of Katz
• This reading is necessary for getting points in
the Studio Activity!
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