Transcript Presentation - ECpE Senior Design

High-Performance FPGA-Controlled Amplifier
Phase IV
April 27th, 2005
May 05-28
Team Information
 Members:
Jimmy Tjoa, EE
 Agus Leonardo, EE
 Ian Overton, CprE
 Client: Teradyne Corporation
 Faculty Advisor: Dr. Chris Chu
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May 05-28
Outline
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Introductory Material
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List of Definitions
Acknowledgement
Problem Statement & General
Solutions
Operation Environment
Intended Users and Uses
Assumptions and Limitations
End Product and other Deliverables
Project Activity Description
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Previous Accomplishments
Present Accomplishments
Approach Considered & Used
Definition Activities
Design Constraints
Research Activities
Design Activities
Implementation Activities
Testing Activities
Other Activities
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Resources and Schedules
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Personnel Effort
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Other Resources
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Financial Requirement
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Schedules
Closing Material
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Project Evaluation
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Commercialization
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Additional Work
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Lessons Learned
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Risk and Management
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Closing Summary
May 05-28
List of Definitions
 Art-work – Copper layer for Printed Circuit Board (PCB)
 Bill of Materials – List of Components and their cost
 DAC – Conversion of a digital signal to an analog sampled
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signal
DC-offset correction – Matched I/O DC-Voltage
FPGA – Field programmable gate arrays, allows us to control
some the circuits automatically
Gain – The ratio of the output amplitude to the input amplitude
Input Impedance – the load placed on the circuit driving an
input
Spectrum Analyzer – A computer-based tool that analyzes
signals in the frequency domain
Q-Value – The distance between the upper and lower frequency
May 05-28
Introduction
 The purpose:
 Design a high-performance FPGA-controlled
amplifier
 Teradyne Corporation will use it for a front-end
spectrum analyzer
 The overall goal:
 Characterize a frequency of up to 100MHz
 Achieve gain of 6dB, 20dB, 40dB, and 60dB
 Low Distortion and Noise
 DC-Offset correction
May 05-28
Acknowledgement
 Teradyne Corporation
 Jacob Mertz
 Eli Roth
 Ramon De La Cruz
 Steven Miller
 Others
 Faculty Advisors
 Dr. Chris Chu
 Dr. Gary Tuttle
 Technical Advisors
 Dr. Randy Geiger
 Dr. Robert Weber
May 05-28
Problem Statement & Solutions
 DC-Offset Correction
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Better DAC
Fix DC-Voltage Range
 Amplifier
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Input Impedance
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Input impedance changes over gains, so a 50Ω load was added
Increase the Q-Values resistors to make a higher impedance without the load
Higher Bandwidth with Lower Distortion and Noise
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Change Q-Values Ratio
Find a better Operational Amplifier
 Lost a Team Member
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Larger Work Load
Removed Frequency Response Calibration
Changed FPGA switching automation to switching manually
 Loss of a Technical Documentation
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Research and Verify Previous General Design
Write up lost Technical Documentation
May 05-28
Operating Environment
 The system should be used in a climate-
controlled laboratory at room temperature
with low humidity.
May 05-28
Intended Users and Uses
 The Teradyne Corporation Engineers
 Educational purposes
May 05-28
Assumptions and Limitations
The design team assumes that:
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End product will not be sold
DC-offset correction turned on and off manually
Gains changed manually
The design team’s limitations are:
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DC-offset voltage kept below ± 1mV
Art-work prototype not be accurate as the circuit fabricated
Cost must not exceed $3000
Input impedance close to 50Ω
Design requirements meet the design specifications
May 05-28
Design Specifications
Input
Total
Input
Voltage
Available
Max Output
Freq Response
Harmonic
Frequency
Range
Gain Settings
Voltage
Flatness
Distortion
Noise
Range
(Volts)
(dB)
(Volts)
(dB)
(dB)
(nV/rtHz)
DC — 1kHz
+/- 5 volts
6, 20, 40, 60
+/- 10 volts
0.05 dB
< - 105 dB
1.5 nV/rtHz
> 1kHz - 20 kHz
+/- 5 volts
6, 20, 40, 60
+/- 10 volts
0.05 dB
< - 95 dB
1.5 nV/rtHz
> 20kHz - 100kHz
+/- 2.5 volts
6, 20, 40
+/- 5 volts
0.10 dB
< -85 dB
2.5 nV/rtHz
> 100kHz - 1MHz
+/- 2.5 volts
6, 20, 40
+/- 5 volts
0.10 dB
< - 80 dB
3.5 nV/rtHz
> 1MHz - 10MHz
+/- 2.5 volts
6, 20, 40
+/- 5 volts
0.10 dB
< - 70 dB
3.5 nV/rtHz
> 10MHz - 20MHz
+/- 2.5 volts
6, 20
+/- 5 volts
0.10 dB
< -65 dB
3.5 nV/rtHz
> 20MHz - 50MHz
+/- 1.0 volts
6, 20
+/- 2.0 volts
0.10 dB
< -50 dB
5.0 nV/rtHz
> 50MHz - 100MHz
+/- 1.0 volts
6, 20
+/- 2.0 volts
0.10 dB
< -40 dB
5.0 nV/rtHz
May 05-28
End Product and Other Deliverables
 Final product will be used as a front-end
spectrum analyzer
 Deliverables
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Simulations for Verification
Final Schematic
Final Art-work
Bill of Materials
May 05-28
Previous Accomplishments
 FPGA code
 General Design
 Operational Amplifier
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Topology
Simulation
May 05-28
Present Accomplishments
 Research & Verification
 Final Schematic
 Final Art-Work
 Bill of Materials
May 05-28
Approach Considered & Used
 PSpice was chosen over Cadence to simulate and verify the two stage
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operational amplifier
 Easy to use
 PSpice models easy to obtain
Art-work was chosen over fabrication for verification
Dip switch was chosen over Mechanical Relays due to insufficient time
The team evaluated the previous work done on the design and
researched if it was the best approach for each subsystem
Modifications on art-work and schematic were done using ExpressPCB
software
Max Plus II will be used to program the FPGA
Amplifiers Considered
 Regular two-stage amplifier
 Special two-stage amplifier
 Regular three-stage amplifier
May 05-28
Special Two-Stage Amplifier
http://seniord.ee.iastate.edu/may0528/01084375.pdf
May 05-28
Definition Activities
 Goals of this project:
 Research & Verify the previous design
 100Mhz gains
 DC-offset correction
 Fabrication
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Frequency response
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Art-work was chosen
Removed due to lost a team member
Testing
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Insufficient time
May 05-28
Design Constraints
 Parts – High quality, precision parts are required to obtain the
specified design requirements for high bandwidth with low noise
and distortion
 Cost – The cost must not exceed $3000 to complete the project
 DC-offset correction – An appropriate design circuit was
assigned
 Approval – Teradyne must approve the design before the
design is implemented
May 05-28
Research Activities
 Study previous team’s design
 Amplifier topology
 Better Components
 New resistor values found
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Removing peaking
Input impedance
Optimized the DAC
May 05-28
Design Activities
 Design schematic and art-work for:
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DC Offset
Operational Amplifier
FPGA
May 05-28
Layout
Implementation Activities
 Art-work
 Schematic
 Add 50Ω Input Load Impedance
 Add Buffer to the output DAC
 Bill of Materials
May 05-28
Testing Activities
 Simulations for operational amplifiers
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Peaking
Input Impedance
Bandwidth
 Simulations for the resistive network in order
to get a correct DC voltage range
May 05-28
Other Activities
 Weekly report
 Team meetings
 Project plan
 Poster
 Design report
 Final report
 Presentation
May 05-28
Resources and Schedules
Personnel Efforts
Jimmy Tjoa
Ian Overton
120
Agus Leonardo
100
80
60
40
20
0
Problem
Definition
Understanding
design
DC-offset
correction
Part numbers
Final Design
Project
Reporting
May 05-28
Other Resource Requirement
Item Team
Team Hours
Cost
Printing of project
poster
20
$ 71.00
Documentations
83
$ 20.00
Board
120
$1343.80
Total
223
$ 770.40
May 05-28
Financial Requirement
Items
W/O Labor
With
Labor($12/hour)
Posters
$ 71.00
$ 311.00
Board
$1343.80
$ 2783.80
Documentations
$ 20.00
$ 1016.00
$ 1434.80
$4110.80
Subtotal
Labor( $12.00 / hour)
Jimmy Tjoa
$1704.00
Agus Leonardo
$2748.00
Ian Overton
$2112.00
Subtotal
$0.00
$ 6564.00
Total
$ 1434.80
$ 10674.80
May 05-28
Project Schedules
May 05-28
Deliverable Schedules
May 05-28
Closure Materials
 Corrected the DC Offset voltage
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Changed resistor network
Added a buffer
 Changed original plan
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Art-work
 Operational Amplifier
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Peaking
Input Impedance
Bandwidth
May 05-28
Project Evaluation
Activities
Accomplishment
Project Definitions
Fully met
Understanding Design
Fully met
DC-offset Correction
Fully met
Part Number
Fully met
Final Design
Fully met
Project Reporting
Fully met
Testing
Not attempted
May 05-28
Commercialization
 Testing Cost: $1343.80
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Art-work
Total part costs
Spare parts
 Actual board cost $442.38
 Recommended street price $600
 Market – consumers who need a high-
performance FPGA-controlled amplifier
May 05-28
Additional Work
 Testing
 Automation using a FPGA using mechanical
relays
 Frequency response calibration
 Fabrication
May 05-28
Lessons Learned
 Team gained a lot of knowledge working on
the design
 Art-work on ExpressPCB
 Integrating new parts into PSpice
 Communication skills with client and faculty
advisor
 Proper documentations
 Team should not depend on work done by the
previous team
 Prepare for losing a team member
May 05-28
Risk and Management
 Lost of a team member
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Work cooperatively and efficiently
Ensure on time delivery
 Simulations might not match the output from
the circuit
 Topology might be wrong so team did more
research
May 05-28
Closing Summary
 Team gained many experiences
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Designing board layout
Researching parts
Team Work
Working for an outside client
Keeping up with technology
Meeting deadlines
May 05-28
Questions ???
May 05-28