Transcript Power Point Document

May 06-14
FPGA Controlled Amplifier
Module (FCAM)
December 8, 2005
Project Team Information

Team Members
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Advisor
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Jesse Bartley, CprE
JiWon Lee, EE
Michael Hayen, CprE
Zhi Gao, EE
Dr. Chris Chu
Client
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Teradyne Corporation
Acknowledgement
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Teradyne Corporation
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Jacob Mertz
Ramon De La Cruz
Steven Miller
Additional Help
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Jason Boyd
Dr. Randy Geiger
Presentation Outline
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Introductory Materials
Technical Overview
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Test Plan
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Amplifier
DC offset correction
Amplifier
DC offset correction
Closing Summary
Purpose & Tasks of the Project
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Purpose:
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To complete and test the FPGA controlled
Amplifier for PC based Spectrum Analyzer
developed by Teradyne
Main Tasks for this team:
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Understand existing design
Board assembly and bring-up
Make detailed test plan
Perform and document tests
Intended Users & Uses
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The primary users:
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Engineers of the Teradyne Corporation
A possibility that a derivative of the device will be
used outside Teradyne in the future.
The product function:
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As a pre-amplifier for the signal input to a PC
based spectrum analyzer device.
PC based spectrum analyzer was design by
previous phase
Assumptions
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The end product will not be sold to other
companies.
The design specifications previously provided
by Teradyne are correct.
The design provided by the previous team is
valid.
Necessary equipment will be available.
End Product & Other Deliverables
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A fully functional and tested design
A functioning prototype
Complete test plans
A full test report
Technical documentation on the design.
Technical Overview
Circuit Overview
Out
In
Two-Stage Op-Amp
-
+
Comparator
DAC
FPGA
Two Stage Op-Amp
Two Stage Op-Amp Overview
-
R3
-
Vi
+
R1
Vo
+
Origin of Design
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Design from Dr. Geiger
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Amplifier with Maximum Bandwidth, Randall LGeiger IEEE,
Operational Amplifier,1970 Minimizing in-Band Harmonics at
Higher Frequencies,
http://seniord.ee.iastate.edu/may0528/01084375.pdf
Chosen by Phase III, May03-10
Reason:

Very Wide Bandwidth
DC-Offset Correction
DC-Offset Correction Overview
R*100
R
comparator
attenuator 1/200
Successive
Approximation
Register
16-bit
DAC
16-bits
FPGA Offset Calculation
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Successive Approximation Register
Input: Comparator output
Checks input, either +/- V
Increments output voltage by +/-38μV
accordingly
Will wait for new comparator output, exact
time to be determined based on SPICE
simulations.
Attenuator
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Output range of DAC: 0-2.5V
Maximum offset of amplifier: -20mV-20mV
Conversion circuit:
-980.4mV
R1
1k
R3
240
0V
V1
-975.7mV
R2
4.02k
V1
R4
0Vdc
-5.000V
-5Vdc
0V
V2
49.9k
Testing and Verification
Testing Design
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Amplifier Testing
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DC-Offset Correction Testing
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Gao, JiWon
Jesse, Michael
Further Constraints
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LabVIEW will be used for automated testing
Extra caution will be taken to avoid damage from
ESD (Electro-Static Discharge)
List of Tests
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Amplifier testing
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PSPICE Simulation Test
Amplifier Gain Test
Harmonic Distortion Test
Amplifier Gain Flatness and Bandwidth Test
DC Offset Testing
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VHDL Behavior Test
DAC Control Test
Offset Calibration Test
Offset Correction Verification Test
Amplifier Testing
PSPICE Simulation Test
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Purpose:
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Verification to the design
Assistance to testing
Simulation:
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Verify design of the amplifier
Determine specifications for gain flatness test
Simulate testing conditions
Amplifier Gain Tests
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Purpose: Ensure the gain requirement of the
amplifier over the specification range
Methodology:107 testing points covering the
whole rang of the Specification
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10 frequency ranges
3 input ranges
4 gain settings
Circuit Parameters
Input
Input
Voltage
Available
Max Output
Frequency
Range
Gain Settings
Voltage
Range
(Volts)
(dB)
(Volts)
DC – 1kHz
+/- 5 volts
6, 20, 40, 60
+/- 10 volts
> 1kHz - 20 kHz
+/- 5 volts
6, 20, 40, 60
+/- 10 volts
> 20kHz – 100kHz
+/- 2.5 volts
6, 20, 40
+/- 5 volts
> 100kHz – 1MHz
+/- 2.5 volts
6, 20, 40
+/- 5 volts
> 1MHz – 10MHz
+/- 2.5 volts
6, 20, 40
+/- 5 volts
> 10MHz – 20MHz
+/- 2.5 volts
6, 20
+/- 5 volts
> 20MHz – 50MHz
+/- 1.0 volts
6, 20
+/- 2.0 volts
> 50MHz – 100MHz
+/- 1.0 volts
6, 20
+/- 2.0 volts
Test Circuit
Signal
Generator
107 input signals
will be applied
LabVIEW automated
ESD Protected
LPF
Amplifier Circuit
(Optional)
Multi-Meter
Harmonic Distortion Test
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Purpose: Test the purity of the output signals
from the amplifier
Methodology:
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High and low point and two end frequencies
Mid-band frequency at middle frequency ranges
10 testing points in total
Specification: The specified parameters are
listed in the next couple of slides
Total Harmonic Distortion
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It is an important measure of the purity of the
output of the amplifier.
Specified Harmonic Distortion
Total
Input
Harmonic
Frequency
Distortion
Range
(dB)
DC – 1kHz
< - 105 dB
> 1kHz - 20 kHz
< - 95 dB
> 20kHz – 100kHz
< -85 dB
> 100kHz – 1MHz
< - 80 dB
> 1MHz – 10MHz
< - 70 dB
> 10MHz – 20MHz
< -65 dB
> 20MHz – 50MHz
< -50 dB
> 50MHz – 100MHz
< -40 dB
Test Circuit
Signal
Generator
Signal at midpoint of each
frequency range
LPF
Amplifier Circuit
(Optional)
Spectrum Analyzer
Amplitudes at certain frequency
points should be observed and
used to calculate the distortion
Amplifier Gain Flatness Test
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Purpose: Ensure the gain flatness requirement of
the amplifier
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Criteria:
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Bandwidth
Gain flatness
Provide stable gain within frequency range
Maintain performance at high frequency
Key equipment: Spectrum Analyzer
Specification: Will be determined by SPICE
simulations
DC-Offset Testing
DC-Offset Correction Tests
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Simulations with Altera’s Quartus II
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Simulate and verify VHDL code
Verify FPGA behavior
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VHDL code matches design
Plays correctly with other components
Performs intended function within spec
DC Offset Specs
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Important Specifications
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Correction to within 1mV
Correct offsets between +20mV and -20mV
Perform calibration within specified time
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To be determined based on SPICE simulations
VHDL Behavior Test
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Verify that code works as intended
Test fixture
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Will simulate analog component of circuit
 Greater than/less than input
 Propagation delay
Calibrates for DAC output value (0-65536)
 Give fixture a number in this range, and the DC-offset
correction should calibrate to correct that value of offset.
Criteria
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Correct calibration
Calibration time within spec
DAC Control Test
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Verify DAC and its FPGA control
Test Fixture
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Sweep range of outputs
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Uses DAC control module to set DAC output
Increments of 1mV (40 data points)
Criteria
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Covers range of +/-20mV
Ensure output is linear
Offset Calibration Test
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Verify entire calibration system
Provide range of DC input voltages
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Cover +25mV to -25mV
Calibrate for each voltage
Measure calibrated output
Time the calibration
Criteria
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(+/-20mV range) Calibrated output within +/-1mV of ground
(outside +/-20mV) Calibrated output within +/-1mV of
maximum corrected value.
Offset Correction Verification
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Final verification of DC-offset calibration with an AC
input signal.
Range of DC offsets will be artificially injected,
forcing correction circuitry to cover its full DC offset
(+/-20mV).
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Calibrate DC offset for each
Measure calibrated output
Provide a range of AC inputs will be provided, covering (0 –
100Mhz)
Measure average output voltage
Criteria:
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Average output must remain within +/-1mV of ground after
calibration
Closing Summary
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This Team’s Tasks
 Assemble the prototype
 Develop FPGA code
 Test the product
 Document all details of the process
Project will make contribution
 Teradyne
 Integrated circuit industry
The team will received the following benefits:
 Technical knowledge
 Team work
 Real industry project
Overall, this project will benefit both the client and the team
Questions