Transcript An Application Engineer’s View

An Application Engineer’s
View
Jonathan Alexander
Applications Consulting Manager
Actel Corporation
MAPLD 2004
Common HDL Coding Errors - 1
 Variable assignments are sensitive to order.
 Variables are updated immediately
 Signal assignments are order independent.
 Signal assignments are scheduled
Process (Clk)
begin
if (Clk’Event and Clk=‘1’) then
Trgt1 <= In1 xor In2;
Trgt2 <= Trgt1;
Trgt3 <= Trgt2;
end if;
end process;Process (Clk)
begin
if (Clk’Event and Clk=‘1’) then
Trgt2 <= Trgt1;
Trgt3 <= Trgt2;
Trgt1 <= In1 xor In2;
end if;
end process;
Signal vTarg3 : std_logic;
Process (Clk)
Variable vTarg1, vTarg2: ...
begin
if (Clk’Event and Clk=‘1’) then
vTrgt1 := In1 xor In2;
vTrgt2 := vTrgt1;
vTrgt3 <= vTrgt2;
end if;
end process;
Process (Clk)
Variable vTarg1, vTarg2 : ...
begin
if (Clk’Event and Clk=‘1’) then
Trgt3 <= vTrgt2;
vTrgt2 := vTrgt1;
vTrgt1 := In1 xor In2;
end if;
end process;
Trgt3
Trgt3
Trgt3
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MAPLD 2004/250A
Common HDL Coding Errors - 2
 Accidental Latch Inferring
 Latches are prone to data corruption due to input glitches, and timing analysis is
quite difficult. Latches should be avoided
 Verilog combinatorial always blocks must always have a “default” statement to avoid
latch inferring
 This especially applies to state machines.
 Example: Without Default Statement:
always @(posedge clk)
begin
state <= statenext;
end
always @(state,data)
begin: my_register
case (state)
2'b00 :
begin
aaa = data;
bbb = 0;
ccc = data;
statenext = 2'b01;
end
2'b01 :
begin
aaa = 1;
bbb = 0;
ccc = data;
statenext = 2'b10;
end
2'b10 :
begin
aaa = data;
bbb = 1;
ccc = data;
statenext = 2'b00;
end
endcase
end //my_register
Alexander
Latches
3
MAPLD 2004/250A
Common HDL Coding Errors – 2
(Cont’d)
 Example: With Default Statement
always @(posedge clk)
begin
state <= statenext;
end
always @(state,data)
begin: my_register
case (state)
2'b00 :
begin
aaa = data;
bbb = 0;
ccc = data;
statenext =
end
2'b01 :
begin
aaa = 1;
bbb = 0;
ccc = data;
statenext =
end
2'b10 :
begin
aaa = data;
bbb = 1;
ccc = data;
statenext =
end
default :
begin
aaa = data;
bbb = 1;
ccc = data;
statenext =
end
endcase
end //my_register
Alexander
2'b01;
2'b10;
2'b00;
Flip-Flops only
2'b00;
4
MAPLD 2004/250A
Testing and Troubleshooting
Techniques - 1
 FPGA Debugging Issue
 FPGA designs typically do not include sophisticated selfdiagnostics
 Pre-defined test point consume I/Os
 Test circuits consume valuable gates
 How to observe and debug FPGA faults?
 Silicon Explorer for Antifuse FPGAs
 Dedicated, built-in architecture gives access to virtually every
internal node in the FPGA
 Nodes can be changed on the fly while device is operating at full
speed
 Up to 4 nodes can be monitored simultaneously
 Uses JTAG input pins for node addressing
 Flexible I/Os can toggle between user output and Probe outputs
 No FPGA gates or routing consumed
 No additional design required
Alexander
5
MAPLD 2004/250A
Testing and Troubleshooting
Techniques – 1 (cont’d)
JTAG
Controller
Column Address
Normal
OE
Sense
Amplifier
C
R
C
C
R
C
R
C
C
R
C
R
C
C
R
Normal
Output
PROBE
Row
Address
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MAPLD 2004/250A
Testing and Troubleshooting
Techniques - 2
Active Probes
 Use active probes when you want to observe signals with
high frequency components (ie noise)
 They provide very low capacitive loading (<1pF)
 Passive probes often will filter high frequency components
 Real-life Example:
 Flip-Flop intermittently double-shifts data.
 Passive probe on external clock did not reveal anything,
however failure never occurred while probing with passive
probes
Alexander
7
MAPLD 2004/250A
Testing and Troubleshooting
Techniques – 2 (Cont’d)
Differential Probes or Signal Subtration
 Differential probes allow users to measure the difference
between two nodes
 Most oscilloscopes allow users to subtract signals to
calculate the difference between two or more nodes
 Both solutions are useful when measuring component
power supply noise with respect to component ground
 VCC alone may not cause an out of spec condition
 GND alone may not cause an out of spec condition
 VCC - GND may exceed spec
 Similar situation can apply when measuring VIN with respect
to Ground (when ground bounce is coincident with
reflections)
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MAPLD 2004/250A