Transcript Status-Week.260

Status – Week 260
Victor Moya
Summary
shSim.
 GPU design.
 Future Work.
 Rumors and News.
 Imagine.
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shSim
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Currently working:
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Command Processor: reads a text based trace file
(programs, parameters, vertexs, commands to
rasterizer).
Shader: simulates a N multithreaded, variable
latency support, VS1 capable ‘vertex’ shader.
Rasterizer: OpenGL ‘emulator’, accepts resolution
and clip planes changes, recieves ‘shaded’ vertexs
from the shader (only 2 QuadFloats, vertex
positon + color), displays the triangles in a GL
window.
shSim
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Tests:
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2/4 multithread (with another 2/4 input buffers)
single shader.
Fixed 3 latency cycles. Shader to Rasterizer
latency of 4. CommandProcessor to Rasterizer
latency of 6.
Simple coordinate change traces (shader.input,
shader.input.2).
Ripple vertex shader example from DX8 & DX9
SDK (ripple.input):
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Around 300 triangles (1100 vertexs).
Color is calculated from vertex position.
shSim
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Ripple.vsh.
shSim
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Screenshots from frames rendered by
shSim:
GPU Architecture
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Based in current GPUs:
NV30
 R300
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Based in other graphic processors:
PS3
 Imagine
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GPU Architecture
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Based in an API:
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DX8
DX9
DX10
OpenGL 1.4 and extensions.
OpenGL 2.0
Based in an architecture model:
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Vector
Scalar
Multithreaded
GPU Specification
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Shader Model:
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Language:
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DX9:
– VS2.0/PS2.0.
– VS3.0/PS3.0.
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OpenGL:
– NV_vertex_program_2/NV_fragment_program.
– ARB_vertex_program/ARB_fragment_program.
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Our own language.
GPU Specification
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Shader Architecture:
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Architectural model:
Scalar.
 SIMD.
 Multithreaded.
 Vector.
 Out-of-order.
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GPU Specification
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Configuration:
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Integer Unit:
– Number.
– Precission.
– SIMD or scalar?
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Float Point Unit:
– Number.
– Precission.
– SIMD or scalar?
GPU Specification
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Memory Unit:
– Number.
– Texture modes.
– Filtering modes.
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Register Banks:
–
–
–
–
Number.
Ports.
Size.
Scalar or SIMD?
XBOX (NV2A) Vertex Shader
Future Work
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Shader:
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Command Processor:
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Add branch/call/ret instructions.
Add texture instructions (Pixel Shader).
Define a trace specification: binary, gzipped?
Define an interface with OpenGL (Mesa?) or
DX8/DX9 (driver?).
Primitive Assembly:
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Implement vertex cache and primitive assembly
(only triangles?).
Implement culling and clipping?
Future Work
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Deferred rendering?
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Transformed geometry must be stored in video
memory.
Geometry must be sorted:
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Tiles.
Front to back.
Rasterization:
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Triangle Setup and Fragment Generation.
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Any suited method: Olano & Greer, DDA?.
MSAA support?
Future Work
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Early Z and Hierarchical Z? Pixel Shader:
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Implement unified with vertex shaders?
Queue/buffering mechanism? (memory/texture
latency very large).
Pixel Shader:
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Unified shader architecture?
Pixels need a lot of buffering (memory/texture
operations).
Implement a TMU simulator (filter algorithms,
memory access, texture compression, cache).
Future Work
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Fixed fragment operations:
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Implement using the shader?
Fog: remove?
Pixel Ownership: remove?
Scissor Test: implement (needed if clipping is not
implemented).
Alpha test: same as Z Test.
Z Test and Stencil Test: must be implemented, but
could be added to a generic shader unit?
Blending: add to shader?
Dithering: remove.
Logical Op: remove or add to shader.
MSAA Operations: ?
Future Work
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Framebuffer:
Z compression.
 Color compression.
 SSAA or MSAA support?
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News and Rumors
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NV30 architecture:
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4x2 pixel pipes?
8x zixel pipes (Z Test & Stencil only).
ATI ready to release R350 and RV350 in a
couple of weeks.
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R350: Updated R300 core with additional features
(?) and increased clock frequency (375 – 400
MHz).
RV350: value chip based in R300 core. Maybe 8x1
core, 128 bits bus. Clock frequency 300 – 400
MHz. 75 Million transistors.
Imagine
‘Computer Graphics on a Stream
Architecture’, John Douglas Owens, PhD
dissertation.
 Not read yet either.
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