Transcript Status-Week.274

Status – Week 274
Victor Moya
Simulator model
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Boxes.
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Perform the actual work.
A box can only access its own data, external data
must come through signals (time!).
The box manages its own signals.
A box:
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whatever you do in 1+ cycle or whatever
or
what a piece of hardware does
Simulator Model
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Signals.
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Communication between boxes.
Carry the simulator time: 1+ cycle latency.
Parameters: bandwidth, latency.
Storage size: bw * (lat + 1).
Not allowed read and write with latency 0.
Simulator Model
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Wiring boxes:
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Global static object.
Creates and binds signals by name.
Statistics
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Global static object.
Boxes declare a statistic name.
The statistics object manages the different
statitistics.
Simulator Model
SignalBinder
BOX
BOX
Box
StatisticBinder
Signal
Signal
Signal
Signal
Statistic
Statistic
Statistic
Statistic
Simulator Model
Box1
Box2
write
read
bw:2
lat: 3
Problems
Must be 0 latency for wires forbidden?
=> NO!
 What happens if a two boxes must
communicate in the same cycle? =>
NOT ALLOWED!.
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Problems
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How to manage multiple instances of the same Box (4
vertex shaders, 8 pixel shaders).
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Create each instance as a different class with its own name
and signal binding.
Box() now has a parameter Name that defines a different
name for each instance (How can we grant the names are
different?).
How to bind signals in multiple instanced boxed (VS, PS).
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Signal are created/binded by the signal emiter and receiver.
Prefix signal name with instance name.
Add new parameters to Box() for the emiters name
instances.
Vertex Shader
VS 1.0 (NV20) based Vertex Shader
model.
 Multithread (multivertex?) supported.
 No branching.
 No texture/vertex buffer load.
 No vertex kill.
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PC
+1
VThread Control
Vertex Shader
+1
Instructions
+1
Vertex Loader
VTIdL
VTId
IR
VTId
VIN0
+
VIN1
VIN2
VIN3
Constants
TMP0
TMP1
TMP2
Address0
Address1
Address2
Address3
TMP3
IR
OP1
OP2
OP3
Swizzle
Negate
ALU
VOT0 VOT1 VOT2 VOT3
Vertex Shader
VS 2.0+ (NV30) based Vertex Shader
model.
 Multithreaded?? Implemented with a
FP array (3DLabs P10).
 Dynamic branching.
 No texture/vertx buffer load.
 No vertex kill.
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+1
VThread Control
+1
VTId
Vertex Shader
VTIdL
PC
PC
PC
PC
STACK
STACK
Instructions
STACK
IR
Vertex
Loader
STACK
+1
VTId
VIN0
VIN1
VIN2
VIN3
TMP0
Constants
TMP1
TMP2
Address0
Address1
Address2
Address3
TMP3
CC
CC
CC
CC
IR
VTId
OP1
OP2
Swizzle
Negate
ALU
VTId
VOT0 VOT1 VOT2 VOT3
OP3
Vertex Shader
VS 3.0 (DX9.1). Not implemented yet.
 Hardware implementation unknown.
 Static and dynamic branching.
 Texture/Vertex Buffer load (and store?).
 Possible vertex kill?
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Vertex Shader Model
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Instruction Fetch
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Decode/Register
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Sends the instruction byte code pointed by the current PC to
Decode/Register box (latency 1).
Calculates next PC (sequential, jump, conditional jump, calls,
return, indirect) and sends it to Instruction Fetch (latency 1).
Reads up to three source operands from the register files (Vertex
Input, Constant, Temporary, Address) and sends them to Execute
with the instruction operation code (latency1).
Gets incoming result (flags + operation result) from execute and
write them in the register files (flags, Vertex Output, Temporary).
Execute
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Performes an operation with the operands received with from the
Decode/Register box and sends the result back to Decode/Register
box with 1+ latency.
loadProgram(code)
Vertex Shader Model
INSTRUCTION FETCH
nextPC(PC)
instruction(iData)
loadConstant(cData)
loadVIn(vData)
DECODE
REGISTER READ/WRITE
vData readVOut()
operation(op, op1, op2, op3)
result (res, flags)
EXECUTE
DirectX 9
Almost ready.
 DX 9 RC 0 just released.
 ATI DX9 demos and drivers.
 GDC Presentations are available already.
 Introduction to VS/PS 3.0 and beyond.
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NV30
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Product ‘release’.
Cards in February.
Reviews in later December.
400-500 MHz.
0.13 um, 125 M Transistors.
FP array implements the vertex shader.
8 pixel pipes, 1 TMU.
128bit 500 MHZ DDRII.