Transcript Document

1
IP integration
from Transistor to Package level
CONSEIL D’ORIENTATION DU GIP CNFM
StMalo 28/11/2012
Speaker name : Philippe Galy
TRD/CCDS/PIMDS/IP-infrastructure
Outline
• Integration context
• Focus on ESD : Events to IP solution
• Package & 3D connections
•Tooling : Checkers & Builders
• Partners & collaborations
Ph Galy JP CNFM 2012
28/11.2012
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3
• Integration context
• Focus on ESD : Events to IP solution
• Package & 3D connections
•Tooling : Checkers & Builders
• Partners & collaborations
Ph Galy JP CNFM 2012
28/11.2012
Context
IP integration question of scale factor
 IP or Macro IP is a complex design
 Integration need to be compliant to package level
Design
Manufacturing
Assembly
System
Different solutions are
offered for our
customers to success
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Context
Manufacturing context
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Complex Process flow
Complex facilities
Etching ; Plasma, RIE , Implantation …
Flavors of substrate : Bulk or PD/FD SOI
200 – 300 mm Wafer
Human
Machine
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Context
Technology context : FEOL
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Thin & Thick oxide gate transistor
High K metal gate
Different topologies ; sub nanometer
Scale down of transistors & metal layers
Flavors of substrate : Bulk or PD/FD SOI
Gordon Moore
Planar MOSFETs
gate
gate
Silicon Substrate
Thin Silicon film
Bulk
FD SOI
20 nm
14 nm
10 nm and beyond
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Technology context : BEOL
Context
 Stack metal : M1 to M11
 Low K inter dielectric
 Complex Stack & Via structure
Sub-Nano
MOS transistor
(FEOL)
Gate stack
Metal Stack
(BEOL)
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Context
IP context
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High Density Memory
Dig/ ANA/ RF IP
LOW leakage IP
GO1/GO2 IP transistors
Multi Applications
1 000 000 000 XTors
High Density Blocks
Complex IO ring
SOC view
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Context
SOC context
Mtr
1000
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Dig/ ANA/ RF SOC
LOW power / FAST SOC
8 CPU/GPU’s, 1-2GHz,
Multi processor
~3-7W, FC,
Multi Applications
6 CPU/GPU’s, 700MHz,
system
~3-6W,
WB,
1 000 000 Trs
on single package
Flip-Chip,
10 CPU/GPU’s,
>2GHz, ~3-7W,
Flip Chip / 3Dstack
Heterogeneous
Apps
System Co-design
FEnd
5 CPU’s, 500MHz
~3-4W, WB,
FE integration
500
PMIC Network
3CPU’s, 250MHz,
~3W,
200 Hierarchical Design,
Wire bonding
28nm FDSOI Available
- 24 nm possible
- Back Bias
- Poly Bias
- Co integration (Bulk + FD SOI)
100
50
90/80 nm
2004-2007
65/55 nm
2005-2010
45/40 nm
2008-2011
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32/28nm
2009-2014
20nm
2012-20xx
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Context
Package context
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Dig/ ANA/ RF
Multi Dice
Multi connections
Thermal behavior
Design/SOC
Assembly
Final Package
Backside view
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Context
System context
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Dig/ ANA/ RF SOC
Power management
Multi Applications
Multi Chips
Multi protocol
Multi standard
Multi environment
Robust solution
Full Plat-Form solution
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• Integration context
• Focus on ESD : Events to IP solution
• Package & 3D connections
•Tooling : Checkers & Builders
• Partners & collaborations
Ph Galy JP CNFM 2012
28/11.2012
ESD event : True life
13
At least four standards are used to qualify a solution
 Human Body Model (HBM)
 Machine Model (MM)
A
30
 Charged Device Model (CDM)
20
 Human Metallic Model (HMM or Gun)
15
HBM IEC 8kV contact
CDM 500V
10
5
0
Different energy stresses: 1A, 2A & 30A
Different stress durations: 1ns to 100ns
t ns
HBM 4 kv
0
20
40
60
80
100 120
MM 200V
Comparison
HBM, CDM, CDM & IEC Stress
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ESD Challenges
ESD context
Chip context
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Digital/Analog/RF and multi powers/Dice
Thin & Thick oxide gate transistor
Scale down of transistors/metal layers
Low power / Fast signal
Multi balls (1000) / multi dice/huge die size (100mm2)
Flavors of substrate : Bulk or PD/FD SOI
ESD Co-design Challenge
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Provide efficient power devices
Provide efficient trigger circuit
Optimize : Silicon area, leakage, parasitic capacitance
Address all ESD standards for all IPs/Ios (RF/ANA/Dig)
Develop Robust & reliable ESD strategy for SOC (IO+core)
Take into account process discrepancy
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Different energy stresses: 1A, 2A & 30A
Different stress duration: 1ns to 100ns
One or Two pins stressed
Can occurs all along the chip lifetime
Perform a Robust Design
thanks to checkers
CCDS
ESD Tools/Checkers Challenge
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10 000 000 instances & more
Checker for IP/IO & core IPs
Pertinent /Robust/portable checkers
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Device Solutions
Different devices are required to address this challenge
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Power device as primary protection
Fast device as secondary protection
Standard device as trigger element
Advanced device as new solution
 Optimize silicon area
 Optimize signal integrity
Don’t forget robust Metal & Via connection
(not discussed here)
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Example : BIMOS transistor
Device Solutions
16
BIMOS Tr = Bipolar + MOS Effects (Theoritical view)
Design solution to catch :
- Dynamic ESD event
- Quasi Static ESD event
TC
R
Dynamic Response
4
3.5
3
2.5
2
1.5
1
0.5
0
0.1
Zener !
0.08
Current (A)
Voltage (V)
0.E+00
Quasi-static Response
(Body + gate bias)
5.E-07
1.E-06
Time (s)
2.E-06
2.E-06
0.06
0.04
Single BIMOS
0.02
0
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1 Voltage
2 (V) 28/11.2012
3
4
Example : Triac power device
Device Solutions
Basic schematics
A1
A1
17
Classic Equations

SCR#2
(*) Equation de Poisson
Gate N
Gate N
 2  q

SCR#1
p  n  N  N a   s
(n, p)
d

(*) Equation de continuité
A2
A2

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
 (n, p)  1
t
q
J n, p U n, p
(n, p)
R_GN=100 Ohms
R_GN=1 Ohm
Current (A)
2
(*) Equation de transport
R_GN_T=100
Ohms
R_GN_T=1 Ohm
1,5
Jn, p  q
(n, p)n, pq
Dn, p(n, p)


(n, p)
(n, p)
1
(*) Equation de la chaleur
Jn, p  q
(n, p)n, p  kn, pT (n, p)  (n, p)T 


(n, p)
0,5
0
0
1
2
3
4
Voltage (V)
5
6
7
8
T  J
 C Si
E   (T )T 
p
Si
(n, p)
 Q

t

Ph Galy JP CNFM 2012

28/11.2012
Example : Beta Matrix
Device Solution
Matrix
Pw
Power device
Concept
Pw
Sub Matrix
Pw
N
P
N
P
N
N
P
N
P
N
P
P+
N+
P
N
P
N
P
N
N+
N
P+
P
N
P
N
P
P
N
P
N
P
N
N
P
N
P
N
P
Pw
Pw
Pw
Cross Section
Pw
P
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A2
A1
A2
Pw
Pw
P+
Pwell
Pw
3D TCAD
N+
P+
N+
Pwell
P+
N+
Pwell
Nwell
Isotherm IV response
Current density extraction
3D TCAD
results
Current (A)
1.5
Extraction
point
1
0.
5
0
0
2
4
6
8 10
Voltage (V)
Ph Galy JP CNFM 2012
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Example : Beta Matrix & HC
Equations set
3D TCAD study

Device Solution
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d

d
d
f (k,r,t ) 
f (k,r,t )  k k f (k,r,t )  r r f (k,r,t )
dt
t
dt
dt

F
(n, p) gi   r (n, p) giun,p  (n, p)  k gi  giCi
t
h

( n, p )   r (n, p ) v  n , p    C  n , p 
t


 J  n , p   q( n , p ) 
( n, p )  U  n , p  
 t

U n , p wn , p
1
3
S n , p   J n , p E 
(n, p )U T  
q
2 t
q( n , p )

n,p

FA
“Hot”
Cross section
Ph Galy JP CNFM 2012
Zoom In
28/11.2012
Trigger Solution
Trigger Circuit :
 Dynamic detection event in the ESD range time
 Static detection event through threshold
 Both detection
 Optimize silicon area
 Fast response
 Low energy behavior
 Designed for the ESD window
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ESD IP Solution
Before
SCR + SCR
After
MOSSWI+ diode
R&D differentiation : Before & After IP integration
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Mosswi
R
C
R
SCR
SCR
C
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Example : HBM+MM+CDM+HMM
Power device + Dynamic Trigger
ESD IP Solution
R
D1
Dual SCR
P1
Silicon measurements
T
C
T
C
IO
T
C
VSS1
IO
T
C
VDD1
IO
VDD2
T
C
Clamp
T
C
VDD1
T
C
P2
R
T
C
New ESD network
Elementary Module
Modular approach
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IO
Clamp
VDD2
VSS2
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ESD Gun
ESD protection strategy
Board/ Chip context
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ESD GUN context
 Energy stress: 30A at least
Digital/Analog/RF and multi powers/Dice
Thin & Thick oxide gate transistor
Multi chips / multi dice / multi balls
Flavors of substrate : Bulk or PD/FD SOI
External connectors/ PCB routing
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Stress duration: 1ns rise time to 100ns
Two pins stressed contact or air discharge
Power off & Power on
Standard : IEC 61000-4-2
ESD Gun Co-design Challenge
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Provide efficient power devices
Provide fast trigger circuit
Optimize : Silicon area,
leakage,
parasitic capacitance
Address all ESD standards (HBM/MM/CDM)
Avoid LU
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ESD CDM
ESD protection strategy
2
1
3
Development of
package model
Identification of the main
phenomenon involved
during stress
Current [A]
Ground plate
RTE
CPM
ST
L1
TEST
W
RAR
CDuC
t
Field plate
RCHR
G
1GW
Evaluation of protection
devices in time range of
CDM
Evaluation of full CDM
protection strategy on IO
4
Development of tools
devoted for CDM study
Static CDM
check on IP
Dynamic CDM
Check on IP block
Kelvin Pad
frame for
VFLTP &
VF TCS
VCD
M
Time [sec]
Basic schematic of the problem to simulate
• Pogo pin contribution
• Package contribution
• Metal contribution
• Design contribution
• Layout contribution
• Substrate contribution
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28/11.2012
ESD CDM
ESD protection strategy
Macro IP
R&D collaboration
Global view of extractions & activities . Link with TDDB
Extract #1
@ 6 ps
Extract #2
@ 249 ps
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Extract #3
@ 326 ps
Extract #4
@ 512 ps
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CDM silicon signatures
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CDM silicon signatures & physical phenomenon :
 Typical CDM silicon signatures identified
 Physical mechanism : Snapback and/or dielectric breakdown
 Examples of signatures see below
Backside view
Filament (hard fail)
Tong effect = Hole +
partial Snapback
Snapback
Snapback
Hole in gate
Drain side
Multi Holes in gate
Hole in gate (Soft fail)
Failure Analysis Item
&
associated expertises
Substrate current
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9-Apr-16
FOCUS
ESD RF & Beyond !
27
Ref : Dimitri Liten ICICDT 2010
Our target
Best Solution
Local clamp
STM C65 SCR+Diode
(15µm x 15µm)
30 GHz
400 MHz
 How to reach the ESD/RF targets
2KV HBM for 20 GHz bandwidth at least
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28/11.2012
ESD RF & Beyond !
Maxwell
Quadri vectors : Aν = (φ,A),
Lorenz gauge : ∂ν
Aν =
R&D collaboration
0
Faraday tensor : Fµν = ∂µ Aν - ∂ν Aµ
Maxwell equation: ∂µ Fµν = - 4п Jν
Vectors :
Silicon
Jν = (ρ,J)
E = -∇φ - ∂t A ,
B = ∇× A
Transport equations :Jn = q μn n (E + vn × B) + k T μn ∇. n
Coupled with Lorenz force
Jp = q μp p (E + vp × B) – k T μp ∇. p
Metal
Continuity equation : ∇· J = - ∂t ρ + U
Transport equation : J = σ.E + μH J × B
Coupled with Lorenz force
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ESD RF & Beyond : Minimize parasitic Capa
29
FEOL + BEOL parasitic capacitance calculation thanks to coupled equations for local
clamp solution
BEOL
Bandwith calculation
FEOL+BEOL extraction
FEOL+ BEOL capacitance
= 80 fF
FEOL
It’s possible to extract E, B fields into the structure (@10GHz)
E(V/m)
Ph Galy JP CNFM 2012
28/11.2012
ESD RF & Beyond !
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Our target
Best Solution
Local clamp
STM C65 SCR+Diode
(15µm x 15µm)
New target
30 GHz
400 MHz
C40,32 demonstrators
How do to ?
Ph Galy JP CNFM 2012
28/11.2012
Beyond : Embedded protection in propagation line
31
Topology
E distribution
RF
Measurements
Model
Hdistribution
Jn distribuition
in Si substrate
Measure
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28/11.2012
R&D collaboration
Metal behavior
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Full 3D ESD device
Current density Time Evolution
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• Integration context
• Focus on ESD : Events to IP solution
• Package & 3D connections
•Tooling : Checkers & Builders
• Partners & collaborations
Ph Galy JP CNFM 2012
28/11.2012
Package & 3D connection
Complexity of package increases with technology node !
 Several layers, material …
 SOC, SIP ….
Pin number
1500 pins
QFP (Quad
Flat Package)
1 000 pins
QFN (Quad
Flat
No-leads)
500 pins
200pins
SOP (Small
Outline Package)
BGA (Ball Grid Array)
64pins
48pins
PGA (Pin Grid Array)
16pins DIL (Dual
In Line)
34
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SIP 3D interconnect
Example of contribution on signal Integrity
 Cu pillar, Ball , TSV 3D interconnect
 Multi substrate package layers
 Interposer …..
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32 nm stacked
on 65 nm Die
TSV
TSV
40GHz
35
Ph Galy JP CNFM 2012
28/11.2012
Transient domain
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• DDR application
• To include BDPROG IO spice netlist
• Load => Memory + Memory Package (POP configuration)
Bump to RDL impact
• Bump RDL impact
IO:BDPROGMOBLPDDRSCARUDQP_URISO_SF_1V2_D
Q_FC_LIN_PHY
Zout=34Ω
ASRCN<6:0> = 0101000
ASRCP<6:0> = 1010101
Spectre models – Typical corners
output_package
input
W,L
IO Spice Netlist
TL model
Package
(SDRDQ2)
Vs
MSub
X pF
Freq = 500MHz
Vhigh = 1V
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• Integration context
• Focus on ESD : Events to IP solution
• Package & 3D connections
•Tooling : Checkers & Builders
• Partners & collaborations
Ph Galy JP CNFM 2012
28/11.2012
IP integration with Flexframe Tool
38
Integration
• Design & topology for example ESD IP
• Flex frame integration and generator tool
ESD
Design …
IPs
(schematic
+ block
layout)
IP IO Offer
Final Delivery
ANA
DIG
SUPPLY
Synchronicity
g
n
d
e
Mtop IO
pin
Special
v
d
d
e
LB IO
pin
STAND
.
Others
…
e
s
d
s
u
b
g
n
d
e
Flexframes
e
s
d
s
u
b
Ph Galy JP CNFM 2012
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CAD/TOPO/EC Checkers Tool
39
Check before/after IP development
• Database environment setup
• Topologic checks : DFM …
• Electric checks : PISI/ESD/ERC/Aging …
• Reports & waivers file
Macro level
Nano level
Ph Galy JP CNFM 2012
28/11.2012
I/O ring builder/checkerTool
40
IO Builder/Checker during development
• Builder/checker IO focused
• Multi engines & thread
• Data Model IP level
• Provide optimized robust solution
Proposed Solution
PLL example Area: 0.62 mm²
Area: 0.21 mm²
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• Integration context
• Focus on ESD : Events to IP solution
• Package & 3D connections
•Tooling : Checkers & Builders
• Partners & collaborations
Ph Galy JP CNFM 2012
28/11.2012
Partners & collaborations
R&D collaborations
• Universities & Laboratories
• Thesis (open positions )
• Internships
• Projects development
• CAD Providers
• National & European projects
• Consortium
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Thank You
Have a Nice Day
Do not hesitate to contact us
Ph Galy JP CNFM 2012
28/11.2012