Transcript Presentation 7 - J-W Lee - Atomic Scale Design Network (ASDN)

Nano and Giga Challenges in Microelectronics
Symposium and Summer School
Research and Development Opportunities
Cracow
Sep. 13-17, 2004
Afternoon 11: Nanotechnology Tool Kit (3:00pm - 6:00pm), Wed., Sep. 15th, 2004
A Compact Model for
Electrostatic Discharge
Protection Nanoelecronics
Simulation
Jam-Wem Lee and Yiming Li
Department of Computational Nanoelectronics, National Nano Device Laboratories
Microelectronics & Information Systems Research Center, National Chaio Tung University
1001 Ta-Hsueh Rd., Hsinchu 300, Taiwan
Introduction
 In nanoelectronics, whole chip ESD protection design is
important for obtaining robust circuits; especially for the
gigascale very large scale integration (VLSI) circuits
 Conventional design methods basically rely on the testkeys
verifications and encounter some unexpected results due to the
ESD events are instantaneously transient behaviors
 Such conventional design method does prolong the time
schedule and trouble the circuit development cycle including
ESD issues
 Any efficient computer aided design (CAD) tools are necessary
for researchers and engineers to design whole chip ESD
protection circuit
Introduction
A Design flow using conventional approach (the left
figure), and the right one is ESD model which includes
SPICE-added design methodology
Introduction
 However, currently existing ESD models are based on the
bipolar junction transistor (BJT) model, such as the Ebers-Moll,
the VBIC, the MEXTRAM, the HICUM, and the Gummel-Poon
models
 These models exploring the pre-breakdown phenomena work
under the normally operation regions, but they can not model
post-breakdown behaviors
 Simulations based on the conventional BJT-based ESD models
for the pre-breakdown behavior is not enough for advanced ESD
modeling
In this paper, a parasitic model specifying the device physics
of the ESD operation is proposed
Introduction
 By considering the geometry effect in the formulation of
snapback characteristics, our model can be directly incorporated
into electronic circuit simulation for whole chip ESD protection
circuit design
 Using an intelligent computational algorithm, the proposed
model and corresponding parameters are calibrated and
optimized with the measured data
 With the developed ESD model, we can investigate robust
enhancement problems and perform a SPICE-based whole chip
ESD protection circuit design in nanoelectronics
ESD Model Formulation
 We can construct the snapback current-voltage (IV) by using
a current controlled voltage source (the breakdown voltage
of parasitic BJT) VBCE, the series resistance caused by Rd
and the external resistance contributed from measurement
instruments Rx. The IV formula is:
V  VBCE
I
( Rx  Rd )
The current controlled voltage source VBCE is expressed as
VBCE  VBCE 0 (1  B 1 ) n
where B is solved from the following equation:
I
I
R( )  ln( )  C  0
B
B
ESD Model Formulation
Equivalent circuit models for the conventional (right
figure) and our (left one) proposed models
R
Z s  re
Vt *  b
ESD Model Formulation
 where R and C can be solved from the following two
auxiliary equations
R
Z s  re
Vt *  b
I
 ln( I s *  b )
Vt
There are only six parameters Rd, n, Zs, re, Is and  b
appearing in the model to be optimized. In the model, Rx
is 50 ohm and Vt is 0.0259 V
The optimization of parameters is performed with the
intelligent computational algorithm
In order to perform ESD robustness simulation on the
whole chip design, ESD model which can satisfy different
scale devices is needed
C  Zs *
ESD Model Formulation
The parasitic BJT works under the two different region, they
are normally operation (low current) and ESD protection (high
current) regions. Those two regions reflect different device
physics
ESD Model Formulation
Shown in the following, we can determine the geometry
ratio as
GR = Max{DW,DL} / Min{DW,DL}
The non-uniform turn-on effect in the
multi-fingers devices
1. The geometry ratio means that,
when GR is equal to 1 that
protection device has the
highest efficiency
2. Contrary, a large ratio leads to
the lower protection efficiency.
Accordingly, the protection
efficiency is proportional to
(GR)ngr; where ngr is a number
between -1 and 0
ESD Model Formulation
 Besides the geometry ratio, the channel length of the
protection device should be also taken into considerations
when constructing the multi-dimensional device model
 The channel length will strongly affect the current gain b of the
parasitic BJT
 Taking b gain into consideration, the turn-on efficiency is
Rd = (L)nl
Combining the previous two geometry related expression,
the turn on resistance Rd is written as
Rd = Rd0 * (GR)ngr * (L)nl
Results and Discussion
 In this work, a 130 nm CMOS process with dual gate oxides
is used in preparing the test devices
 For the ESD damages are always occurred at the
input/output (I/O) devices, therefore, the thick oxide devices
are usually used in designing the ESD protection circuit
 In order to obtain a better match with the realistic situation
of the ESD protection circuit design, the I/O devices with a
gate-oxide thickness of 7.0 nm and the gate length of 440
nm is firstly prepared in this experiment
 Transmission line pulse (TLP) system is used in measuring
the snapback IV characteristics and verifying the ESD
robustness simultaneously
Results and Discussion
The transmission line pulse system used in this experiment
Results and Discussion
The optimized parameter for our model
Results and Discussion
Comparison of the measured (dish line) and the simulated
(solid line) results
Results and Discussion
Optimization of the geometry ratio effect (ngr = 0.84)
Results and Discussion
Optimization of the channel length effect (nl = -0.24)
Conclusions





An ESD equivalent circuit model for deep-submicron and
nanoscale semiconductor device simulation has been
developed
This model accounts for the snapback characteristics
and can be directly implemented into nanoelectronic
circuit simulation
Using the measured data, physical properties and
geometry effects have been modeled and optimized in
the proposed model
Simulation and comparison have demonstrated good
accuracy of the proposed model
Mathematically, this ESD model is continuous and can be
incorporated into SPICE-compatible circuit simulators to
perform ESD simulation in nanoelectronics.
Thank you for your attentions!