Transcript Asynchronous Primitives in CML

Asynchronous Primitives in CML
High-Speed and Low-power VLSI
97.575
Winter 2003
Professor: M. Shams
Prepared by: Masoud Mashhouri
Introduction
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In this presentation, CML gates and
their advantages and disadvantages are
discussed.
Also, a summary of a brief description
of Asynchronous circuit is presented.
It is the main goal of this project to
integrate the CML primitives into
Asynchronous circuits.
Virtues of CML
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Due to less number of PMOS transistors the input capacitance of
these gates is lower than conventional CMOS. Therefore the
speed is higher.
And,…the area is also much smaller than conventional CMOS.
Switching Noise non-existent, therefore the ground bounce is
minimized. This is ideal for High-Frequency Application.
Draw-Backs
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It has a constant power dissipation due
to the continuous current through the
current source.
Cascading is difficult due to the low
output driving power.
CML Basic Elements
[Ref. 2]
Modified CML Basic Elements
Inverter
Type (1) Inverter
Type (2) Inverter
[Ref. 1]
Modified CML Universal Gates
Type (1) Universal Gate
Type (2) Universal Gate
[Ref. 1]
Modified CML Basic Elements
D-Flip-Flops
Type(1) D-Latch
Type(2) D-Latch
Asynchronous Circuit
1.
2.
3.
4.
5.
6.
7.
Asynchronous Circuit have better
performance. Among all other advantages,
we can list:
No power dissipation when circuit is Idle.
No Clock network
No concern about clock skew
No power dissipation due to a clock network
Noise Immunity
Modularity
Technology Migration is easier in Asynchronous
circuits.
Asynchronous Circuit
Configurations
Four - 
Request
Sender
Receiver
Acknowledge
Four -  Timing Diagram
Request
Request
Acknowledge
Sender
Receiver
Phases
Data
Data
Acknowledge
Two - Timing Diagram
Phases
Acknowledge
Request
Request Acknowledge
1
Sender
Data
0
Receiver
Primitives of Asynchronous Circuits
a
WIRE
b
IWIRE
b
a
JOIN
a
c
b
a
b
MERGE
M
MERGE
a
c
b
c
Implementation of “JOIN”:
C-Elements (Truth Table)
Input A
Input B
Low
Low
Low
High
High
Low
High
High
Output
High
Previous
State
Previous
State
Low
Implementation of “JOIN”:
C-Elements (State Diagram)
a
b
JOIN
c
[Ref. 3]
C-Elements and Its Implementations
(CMOS)-1
Sutherland’s Circuit
C-Elements and Its Implementations
(CMOS)-2
Van Berkel’s Circuit
Martin’s Circuit
[Ref. 4]
Project Schedule
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April 1-7:Study, Preparation and
Preliminary Design.
April 8-19: Final Design,Testing and
Simulation.
April 20-28: Project Finalizing and
Report preparation.
May 5: Project Final Presentation.
Conclusion
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In this presentation a brief description
of CML and Asynchronous circuits were
discussed.
This presentation provides the
background for the project at hand.
References
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1.Kamran Irvani, Farshid Saleh, et. Al.
“ Clock and Data
recovery for 1.25 Gb/s Ethernet Transceiver in 0.35 µm CMOS”.
2.Jason Musicer, M. Eng. Thesis.
3.Maitham Shams, et al, “Asynchronous Circuits”.
4.Maitham Shams, et al, “ A Comparison of CMOS
Implementations of an Asynchronous Circuit Primitive: the CElement”.