Transcript Transformational Partitioning for Co

System Timing
Mark B. Josephs
South Bank University, London
[email protected]
A. A. Jerraya
Thematic Area Definition
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Research topics
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asynchronous circuit design, arbitration, metastability
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clocking schemes, synchronization, skew
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mixed timing circuits, synchronous/asynchronous interfaces
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globally-asynchronous locally-synchronous systems
Research communities
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IEEE Async international symposia
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ACM/IEEE Tau workshops
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European ACiD-WG workshops + summer schools
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DATE A6 (also B1 B5 B6 B10)
System Timing
EuroSoC, March 2003 - 2
Paradigm Shift
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Increasingly heterogeneous organization of SoC
timing
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dominance of interconnect delay over gate delay
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(e.g. multiple clock cycles required for signal to cross chip,
impractical to distribute clock across entire chip)
rapid growth of design reuse (e.g. blocks from different
design houses, blocks conforming to standardized off-chip
interfaces)
Need for better management of power consumption,
noise and EM radiation caused by digital circuits
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System Timing
high-performance systems (e.g. cooling problem)
mixed-signal systems (e.g. voltage noise generated on
power-supply lines or currents induced in substrate affect
A/D conversion, radiation mistaken for radio signal)
secure systems (e.g. data-dependent power consumption
and timing reveals information stored on smartcard)
EuroSoC, March 2003 - 3
Current Status and Barriers to Overcome
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Current status
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one company (Philips) marketing asynchronous lowpower products (designed using concurrent
programming language and associated tools)
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several (Intel, Sun) using asynchronous techniques
within mainly synchronous products
several startups (Theseus, Fulcrum, Self-Timed
Solutions) offering asynchronous design flow
powerful asynchronous logic synthesis tools
emerging from academia (UPC, Columbia)
industry and academia experimenting with GALS
design
Barriers to Overcome
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System Timing
global-clocking is tried and trusted
system-timing methodologies need to be integrated
into standard design flows
EuroSoC, March 2003 - 4
Tasks
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Long term vision
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On-chip modules are islands of self-timed functionality
(e.g. implemented in asynchronous logic, or locally-clocked with
asynchronous wrapper)
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Asynchronous structures provide on-chip interconnect
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(e.g. asynchronous FIFOs and switches)
Communications-centric EDA (e.g. verification, synthesis and
test without global-clock strait-jacket)
Tasks for the first 18 months
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System Timing
organize EuroSoC workshop on system timing
participate in other EuroSoC workshops (e.g. on network-onchip, design methods & IP reuse, formal methods)
consolidate and extend knowledge (about circuit techniques
for synchronization and global signaling, heterogeneous timing in
standard design flows, formal verification and synthesis of
asynchronous logic)
organize EuroSoC summer school on system timing
EuroSoC, March 2003 - 5