Transcript Introducing
FaStack Technology A Look at Various 3D Applications, Their Designs, and Ultimate Silicon Results Tezzaron Semiconductor 3D Stacking Approaches Chip Level Amkor : 4S CSP (MCP) Transistor Level Matrix: Vertical TFT Wafer Level Competitors : Conceptual • Infineon/IBM • RPI • Ziptronix • ZyCube • TruSi • Xan3D/Vertical Circuit/Tessera Tezzaron: Actual Irvine Sensors : Stacked Flash Tezzaron: 3 wafer stack Density gain : “Yes” Cost impact: “Expensive” Speed gain: “Zero or Negative” Reliability: “No” Multi-Func: “Limited” : “Limited” only for PROM : “Expensive” due to low yield : “Extremely slow” : “No” : “No” Tezzaron Semiconductor : “Yes” : “Cost effective” : “Extremely fast” : “yes” : “yes” Wafer Level Stacking Approaches Infineon/IBM Infineon : W deep via RPI/ Ziptronix/ ZyCube RPI : Dielectric bonding Ziptronix : Covalent bond (4-inch) Tezzaron Tezzaron : Copper bonding Backside of the stacked wafer IBM : SOI wafer thinning ZyCube : Injection glue bonding 3 wafer stack Impediments: • Sliced wafer handling • Alignment budget • Uniform bonding • Film stress during deep via fills • Wafer warp • Heat dissipation Impediments: • Large alignment errors • Strength/uniform bonding, voids • Peeling propensity during thinning • Film stress during deep via fills • Wafer warp • Heat dissipation Tezzaron Semiconductor 3D Sensor “All key elements; Alignment, Bonding (Uniformity & Strength), Low thermal budget ( <400C), Si thinning (Control & Uniformity), Limiting stacking yield losses, Facile heat dissipation of wafer level stacking have been simultaneously integrated to meet market demand for density, cost and speed” The Objective Tezzaron Semiconductor “It is clearly seen in Figure 1, that without further reductions in interconnect delay, reducing gate dimensions much below 130nm do not result in corresponding chip improvements.” NSA Tech Trends Q3 2003 Tezzaron Semiconductor Denser! Tezzaron Semiconductor Faster! Shorter Wires td 0.35 x rcl2 Propagation delay is proportional to: Tezzaron Semiconductor 1 # of layers • Global Interconnect “problem” • Span of Control Tezzaron Semiconductor Lower Power! Poweravg = Capacitancetot x Voltage2 x Frequency Therefore: Poweravg Capacitancetot Capacitance is mostly due to wires. Stacked wire length 1 # of layers Therefore: Poweravg stacked Poweravg single layer # of layers Tezzaron Semiconductor Lower Costs! • • • • • Less processing per layer Better optimization per wafer Higher bit density (memories) Lower test cost (using Bi-STAR™) Higher yield (using Bi-STAR™) Tezzaron Semiconductor