Transcript Digital Systems - University of Waikato

Digital Devices
Digital Devices
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Implementing logic circuits
Shorthand notation
Electrical characteristics
Implementing Logic Circuits
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There are several varieties of transistors – the
building blocks of logic gates – the most
important are:
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BJT (bipolar junction transistors) – one of the first to be
invented.
Now largely supplanted by FET (field effect
transistors), in particular Metal-oxide semiconductor
types (MOSFET’s).
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MOSFET’s are of two types: NMOS and PMOS
TTL and CMOS
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Connecting BJT’s together gives rise to a family of logic
gates known as TTL
Connecting NMOS and PMOS transistors together gives
rise to the CMOS family of logic gates.
BJT
transistor types
TTL
logic gate families
MOSFET
(NMOS, PMOS)
CMOS
Electrical characteristics
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TTL
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faster
strong drive capability
CMOS
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lower power consumption
simpler to make
greater packing density
better noise immunity
•Complex ic’s contain many millions of transistors.
•If constructed entirely from TTL type gates would melt
•A combination of technologies may be used.
•CMOS has become most popular and has had greatest
development
Electrical characteristics of logic families
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Important characteristics are:
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VOHmin min value of output recognised as a ‘1’
VIHmin min value input recognised as a ‘1’
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VILmax max value of input recognised as a ‘0’
VOLmax max value of output recognised as a ‘0’
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Values outside the given range are not allowed.
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logic 1
indeterminate
input voltage
logic 0
Noise Margin
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If noise in the circuit is high enough it
can push a logic 0 up or drop a logic 1
down into the “illegal” region
This is the magnitude of the voltage
required to reach this level is the noise
margin
Noise margin for logic high is:
NMH = VOHmin –
VIHmin
Vohmin
logic 1
Vihmin
indeterminate
input voltage
Vilmax
logic 0
Volmax
Further Important Characteristics
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The propagation delay (tpd) which is the time taken for
a change at the input to appear at the output
The fanout, which is the maximum number of inputs
that can be driven successfully to either logic level
before the output becomes invalid
TTL - Example SN74LS00
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Recommended operating conditions
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Vcc supply voltage
input voltages
5V ± 0.5 V
VIH = 2V
VIL = 0.8V
Electrical Characteristics
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5 Volt
Input
Range
for 1
output voltage (worst)
VOH = 2.7V
VOL = 0.5V
Maximum input currents
IIH = 20µA
IIL = -0.4mA
propagation delay
tpd = 15 nS
noise margins
Fan-out
for a logic 0 = 0.3V
for a logic 1 = 0.7V
20 TTL loads
Output
Range
for 1
2.7
2.0
Input
Range
for 0
0.8
0.5
0 Volt
Output
Range
for 0
Electronic Combinational Logic
Within each of these families there is a large variety of different
devices
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We can break these into groups based on the number gates per
device
Acronym
Description
No Gates
Example
SSI
Small-scale integration
<12
4 NAND gates
MSI
Medium-scale
12 – 100
Adder
LSI
Large-scale
100 – 1000
6800
VLSI
Very large-scale
1000 – 1m
68000
ULSI
Ultra large scale
> 1m
486/586
For this course we will just look at the first 2: SSI and MSI
SSI Devices
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Each package contains a code identifying the package
N74LS00
Manufacturers Code
Family
L
LS
H
N = National Semiconductors
SN = Signetics
Specification
Member
00 = Quad 2 input NAND
02 = Quad 2 input Nor
04 = Hex Invertors
20 = Dual 4 Input NAND
Connections on 74LS00
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Show how a single 74LS00 could be used to
implement the function
P = A.B+A.C
14 13
1
2
12
11
10
9
8
3
4
5
6
7
Connections on 74LS00
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Can be done in three steps:
Draw the equivalent circuit
Convert to NAND gates only
Work out the pin connections
Pin Connections
14 13
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A connects to 1,2 and 13
B connects to 12
C connects to 5
Outputs
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11
10
9
8
3
4
5
6
7
One solution, check it!
Inputs
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12
P connects to 8.
Pins
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11 to 10
3 to 4
6 to 9
1
2
MSI Devices
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Commonly used functions such as the adder and the
BCD-to-seven-segment display are implemented as
MSI devices
BCD inputs
outputs to segments
BCD to SSD
Programmable Logic Devices
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Programmable devices have their functionality
programmed before they are first used.
Range in complexity from 100’s to 10,000’s of
logic gates.
PLD’s
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Commonly use logic gates based on diodes:
Vdd – logic 1
eg AND gate
Ry
a
both at logic 1
b
y = a.b
if either a or b is pulled down to Vss,
logic 0, then y is pulled to zero also
More inputs can be made by adding more diodes.
Source: Bebop to the Boolean Boogie, Clive Maxfield, Technology Publishing, ISBN 1-878707-22-1
Exercise
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Consider how an OR gate might be implemented:
a
b
Ry
a and b are at logic ?
output y is on upper or lower
line
Vdd – logic 0
Fusible link PLD’s
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Each diode has an associated link (fuse)
The can be “blown” with a high voltage pulse
Thus the arrays of diodes can be programmed
(one-time).
PLD’s
Inputs
Most of these devices
are based on a two
level structure
(sum of products
form).
AND
plane
products
OR
plane
outputs
In practice this might be represented as:
inputs
A B C
The
fusible links are
made at the x’s,
otherwise blown.
PLD notation
D
A.C + B.C
outputs
D + A
Inverted inputs
inputs
A
B
A.B + A.B
= B
outputs
A + B
PLD’s
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The main types of PLD include:
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PLA’s (programmable logic arrays)
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PAL’s (programmable array logic)
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PROM’s (programmable read only memory)
PLA’s
A
A programmable logic array (PLA)
has all links programmable in both
AND and OR arrays.
Very flexible.
Many applications don’t require
such flexibility
B
PALs
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AND plane
programmable
OR plane fixed
Not so flexible
Operate faster
because hardwired OR’s switch
quicker than
programmed links.
AABB
A
F4
F1
1
3
B
P
2
F5
F8
programmable links
PAL’s
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P = A.notB + notA.B
Use gate 1 to
implement the 1st
product term and
gate 2 to implement
the second
First term blow F2
and F3
Second term blow F5
and F8
AABB
A
F4
F1
1
3
B
2
F5
F8
P
PALs Shorthand Notation
A B CD E
P
P = A.C.D
PROMs
data
address
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AND array is pre-defined
OR array is programmable
Output of AND plane contains a
signal for each of the possible
input combinations
Memory device where each
address applied to inputs returns
a programmed value
ROM
PROM
A
B
address 0
address 1
address 2
address3
programmable OR array
PROMs
Example: The full adder
Cin
0
0
0
0
1
1
1
1
A
B
S
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
Cout
0
0
0
1
0
1
1
1
Cin
A
B
111
110
101
decoder 100
011
010
001
000
sum
Cout
Reprogrammable PLD’s
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EPROMS are like PROM’s except that they can be reused.
Ultra-violet light is used to restore the fusible links
This is shone through a quartz window on top of the
chip
Useful for testing and debugging before PROM’s are
manufactured.
Custom and Semi-custom Integrated
Circuits
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Custom Chips: where the chips are designed
from scratch
Very time consuming and expensive (Need to
manufacture >105 to be economic)
Semi-custom Chips: where most of the design is
already done and designer only has to make the
final connections
What you should be able to do:
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State the principal characteristics of TTL and CMOS logic
gate families.
Define key terms such as:
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fan-out
propagation delay
noise margin
Describe the key features of the range of PLD’s: PLA,
PAL, PROM.
Convert a (simple) shorthand PAL diagram to a logic
expression.