Transcript Document

Design, Fabrication, and Testing a Four- Quadrant Silicon Photosensor
Student: Tho T. Snow
Advisor: Prof. Mustafa G. Guvench
Electrical Engineering Department - University of Southern Maine
A four-quadrant Si photosensor is designed to fabricate on a 4-in n-type wafer manufactured by Fairchild Semiconductor
Top view of 3 masks designed for a four-quadrant Si photosensor
Structural cross sectional view of a
quadrant of Si photosensor device
Mask # 1
Mask #2
Mask #3
Top view of
p++ active layer
Metal contact
to active layer
Metallization
pattern
three masks aligned
on top of each other
The goal of this project is to design and fabricate a Si photosensor consisting of four identical
photodiodes placing in a square pattern on a Si chip. The photosensor will be used to sense the 2dimension position of the chip with respect to the spot defined by Red 632.8 nm He-Ne laser beam.
Inverse-Capacitance-Squared Curve
Capacitance (pF)
Capacitance versus Bias Voltage
Cmax = 330 pF
300
200
100
0.0
20.0
Bias voltage (V)
The photo above is the
vacuum chamber used in
the metal deposition on the
surface of the Si wafer. The
metal layer on the wafer
shown in the picture above
was processed using this
vacuum chamber
200
150
40.0
60.0
100
slope =
90
0
-20.0
Picture on the left hand
side is the control unit of
the furnace, and the one
on the right is a hot
furnace tube in which the
wafer is placed for oxide
growth and dopant
diffusion.
250
ICS (1/nF)^2
400
50
0
-15.0
-10.0
-5.0
Bias Voltage (V)
0.0
This is the
Curve Tracer
used in the IV curve
plotting and
testing of the
photodiode.
The oxide thickness and the doping concentration of the Si
layer underneath the oxide can be determined using
capacitance versus bias voltage measurements as shown. And
the deposited metal thickness can be determined using the four
point resistance probe test