Transcript Lect3-performance_cont

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CPS3340
COMPUTER ARCHITECTURE
Fall Semester, 2013
Lecture 3: Computer Performance
Instructor: Ashraf Yaseen
09/03/2013
DEPARTMENT OF MATH & COMPUTER SCIENCE
CENTRAL STATE UNIVERSITY, WILBERFORCE, OH
Review
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


Last Class

Definition of Computer Performance

Measure of Computer Performance
This Class

Computer Performance

Power Wall

Assignment 1
Next Class

Computer Logic

Boolean
Performance Summary
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The BIG Picture
Instructio ns Clock cycles
Seconds
CPU Time 


Program
Instructio n Clock cycle

Performance depends on
 Algorithm:
affects IC, possibly CPI
 Programming language: affects IC, CPI
 Compiler: affects IC, CPI
 Instruction set architecture: affects IC, CPI, Tc
§1.5 The Power Wall
Power Trends
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
In CMOS IC technology
Power  Capacitive load  Voltage 2  Frequency
×30
5V → 1V
×1000
Reducing Power
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
Suppose a new CPU has
 85%
of capacitive load of old CPU
 15% voltage and 15% frequency reduction
Pnew Cold  0.85  (Vold  0.85) 2  Fold  0.85
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

0.85
 0.52
2
Pold
Cold  Vold  Fold

The power wall



We can’t reduce voltage further
We can’t remove more heat
How else can we improve performance?
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Constrained by power, instruction-level parallelism,
memory latency
§1.6 The Sea Change: The Switch to Multiprocessors
Uniprocessor Performance
Multiprocessors
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
Multicore microprocessors
 More

than one processor per chip
Requires explicitly parallel programming
 Compare
with instruction level parallelism
 Hardware
executes multiple instructions at once
 Hidden from the programmer
 Hard
to do
 Programming
for performance
 Load balancing
 Optimizing communication and synchronization
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

Yield: proportion of working dies per wafer
http://www.youtube.com/watch?v=-GQmtITMdas
§1.7 Real Stuff: The AMD Opteron X4
Manufacturing ICs
AMD Opteron X2 Wafer
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

X2: 300mm wafer, 117 chips, 90nm technology
X4: 45nm technology
Integrated Circuit Cost
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Cost per wafer
Cost per die 
Dies per wafer  Yield
Dies per wafer  Wafer area Die area
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Yield 
(1  (Defects per area  Die area/2)) 2

Nonlinear relation to area and defect rate
Wafer cost and area are fixed
 Defect rate determined by manufacturing process
 Die area determined by architecture and circuit design

SPEC CPU Benchmark
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
Programs used to measure performance
 Supposedly

Standard Performance Evaluation Cooperative
(SPEC)
 Develops

typical of actual workload
benchmarks for CPU, I/O, Web, …
SPEC CPU2006
 Elapsed
time to execute a selection of programs
 Negligible
I/O, so focuses on CPU performance
 Normalize
relative to reference machine
 Summarize as geometric mean of performance
ratios
 CINT2006
(integer) and CFP2006 (floating-point)
CINT2006 for Opteron X4 2356
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IC×109
CPI
Tc (ns)
Exec time
Ref time
SPECratio
Interpreted string processing
2,118
0.75
0.40
637
9,777
15.3
bzip2
Block-sorting compression
2,389
0.85
0.40
817
9,650
11.8
gcc
GNU C Compiler
1,050
1.72
0.47
24
8,050
11.1
mcf
Combinatorial optimization
336
10.00
0.40
1,345
9,120
6.8
go
Go game (AI)
1,658
1.09
0.40
721
10,490
14.6
hmmer
Search gene sequence
2,783
0.80
0.40
890
9,330
10.5
sjeng
Chess game (AI)
2,176
0.96
0.48
37
12,100
14.5
libquantum
Quantum computer simulation
1,623
1.61
0.40
1,047
20,720
19.8
h264avc
Video compression
3,102
0.80
0.40
993
22,130
22.3
omnetpp
Discrete event simulation
587
2.94
0.40
690
6,250
9.1
astar
Games/path finding
1,082
1.79
0.40
773
7,020
9.1
xalancbmk
XML parsing
1,058
2.70
0.40
1,143
6,900
6.0
Name
Description
perl
Geometric mean
11.7
n
n
Execution time ratio
i1
i
SPEC Power Benchmark
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
Power consumption of server at different workload
levels
 Performance:
ssj_ops/sec
 Power: Watts (Joules/sec)
 10
  10

Overall ssj_ops per Watt    ssj_ops i    poweri 
 i0
  i 0

SPECpower_ssj2008 for X4
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Target Load %
Performance (ssj_ops/sec)
Average Power (Watts)
100%
231,867
295
90%
211,282
286
80%
185,803
275
70%
163,427
265
60%
140,160
256
50%
118,324
246
40%
920,35
233
30%
70,500
222
20%
47,126
206
10%
23,066
180
0%
0
141
1,283,590
2,605
Overall sum
∑ssj_ops/ ∑power
493
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
Improving an aspect of a computer and expecting a
proportional improvement in overall performance
Timprov ed 

Example: multiply accounts for 80s/100s


Taf f ected
 Tunaf f ected
improvemen t factor
How much improvement in multiply performance to
get 5× overall?
80
 Can’t be done!
20 
 20
n
Corollary: make the common case fast
§1.8 Fallacies and Pitfalls
Pitfall: Amdahl’s Law
Fallacy: Low Power at Idle
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
Look back at X4 power benchmark
 At
100% load: 295W
 At 50% load: 246W (83%)
 At 10% load: 180W (61%)

Google data center
 Mostly
operates at 10% – 50% load
 At 100% load less than 1% of the time

Consider designing processors to make power
proportional to load
Pitfall: MIPS as a Performance Metric
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
MIPS: Millions of Instructions Per Second
 Doesn’t
account for
 Differences
in ISAs between computers
 Differences in complexity between instructions
MIPS 

 CPI
Instructio n count
Execution time  10 6
Instructio n count
Clock rate

6
Instructio n count  CPI
CPI

10
6
 10
Clock rate
varies between programs on a given CPU
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
Cost/performance is improving
 Due

Hierarchical layers of abstraction
 In

both hardware and software
Instruction set architecture
 The


to underlying technology development
hardware/software interface
Execution time: the best performance measure
Power is a limiting factor
 Use
parallelism to improve performance
§1.9 Concluding Remarks
Concluding Remarks
Summary
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


Performance Definition
Power Trend
Amdahl’s Law
What I want you to do
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
Review Chapter 1
Work on your assignment 1