Transcript Introduction to Transistors

Introduction to Transistors
Objectives of Lecture
1. Review of Depletion Regions and IV curves
2. Description of PN, NPN and PNP Junctions and the different types of
transistors produced
3. Explain how Bipolar Transistors work
4. Describe the characteristics of a MOS Transistor
5. Explain how to bias a MOS transistor
6. Be able to derive the Drain-Source current calculations and understand the
voltage conditions required for both saturated and unsaturated conditions
of operation
7. Be able to explain how an inverter works
8. Explain what CMOS is and why it is preferred over NMOS only circuits
9. Know how an SRAM Cell works
10. Be able to explain how Parasitic Capacitances are formed and why they
cause problems
11. Describe what CMOS Latchup is and how it forms
Ruth Doyle - Intel Ireland
Depletion Regions and IV Curves
• Semiconductors are materials which are insulators at zero kelvin
but have a small amount of intrinsic conduction at room
temperature. They are group IV materials on the periodic table.
• The can be doped with elements from group III and group V to
increase their conductivity.
• When silicon which has been doped n-type is contacted to silicon
which has been doped p-type a pn junction is formed.
• A depletion region is formed at the junction where excess n and
p type carriers neutralise each other.
• Applying a voltage such that the device is forward bias will cause
the depletion region to shrink which applying it in reverse bias
will initially expand the depletion region until breakdown ois
reached at a high voltage.
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PN Junction = Diode
… and what that looks like mathematically…
ID
I D = I S (e
IDEAL
qVA/KT
- 1)
REAL
Forward Bias
What current would
look like in reverse
bias if junction
didn’t break down VBD
0 0.5 1.0 1.5 2.0 2.5
Junction
JUNCTION
Breakdown,
BREAKDOWN
what happens
in real life
Reverse Bias
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3.0
VD
Delay in current
increase until
overcome barrier of
depletion region.
NPN/PNP Junctions
• There are several ways in which two PN junctions can be
connected to each other.
• Two typical methods produce the MOS transistor and the
bipolar transistor.
• The two transistors are used extensively in IC design because of
their different characteristics.
Gate
Source
Base
Drain
N+
Emitter
Collector
N+
N
P
MOS Transistor
P
N
Bi-Polar Transistor
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Bi-Polar Transistors
• The three components are the Emitter (E), Base (B) and
Collector(C).
• The gate is connected to the Semiconductor (produces heat)
• Quiescent State: Emitter/Gate at same bias. No current. E/B
current is limited by intrinsic field, B/C junction is reversebiased.
• Conducting State: VE < VB << VC (NPN type)
– Emitter/Base = Forward Biased. Base/Collector = Reverse
Biased.
– This Bias is the same as for MOS device.
– Emitter/Base field extends almost to Collector. Forward bias
injects minority carriers into narrow Base. These carriers
immediately drift to B/C junction, and the B/C electric field
accelerates them into Collector.
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Bi-Polar Transistors
• The NPN junction shown below is a basically two diodes.
• The np junction on the emitter side (emitter base) is in forward
bias while the pn junction on the collector side (base collector)
is in reverse bias.
ID
qVA/KT
I D = I S (e
- 1)
IDEAL pn junction the constant reverse saturation
• In a reverse biased
REAL
current is largely
independent of the bias voltage.
• However the rate of injection of charge carriers can be
controlled by the forward biased np junction.
VBD
0 0.5 1.0 1.5 2.0 2.5
JUNCTION
BREAKDOWN
Emitter
N+
P
Base
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3.0
VD
Constant reverse saturation
N
current
independent of bias
voltage
Collector
• To explain the workings of the bi-polar transistor its more
useful to look at it in terms of energy levels.
N
Emitter
P
N
Base
Collector
• In each of the N-type layers conduction can take place by the
free movement of electrons in the conduction band.
• In the P-type layer conduction can take place by the movement
of the free holes in the valence band.
• In the absence of any externally applied electric field, depletion
zones form at both PN-Junctions, so no charge moves from one
N layer to the other .
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• When a reverse bias voltage is applied between the base and
collector the energy bands change as such,
N
P
N
Large V
• The polarity of the applied voltage widens the depletion region
between the collector and base and so no current will flow.
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• If a voltage is now applied to the emitter and base which
forward biases this junction, the following happens to the
energy bands and current flow.
N
P
N
Large V
Small V
• Electrons are pushed from the emitter into the base region. Once
there the electrons can respond to the attractive force from the
positively-biased collector region.
• The result is an emitter-collector current whose magnitude is set
by the chosen emitter-base voltage we have applied.
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• Some of the electrons from the emitter will end up recombining
with a hole in the base.
N
IB
P
Small V
N
IE
Large V
• The result is that the base loose some of its positive charge. This
needs to be replenished to ensure the base does not become more
negative (and prevent electron flow).
• The emitter-base voltage removes captured electrons to maintain
hole numbers. A current flows then in this part of the circuit that is
about 100 times smaller than the base collector current
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• So in the configuration shown here the emitter side of the
device injects electrons into the base which are then collected
to yield the collector current.
• For a good bi-polar transistor almost all of the electrons
injected into the base should be collected by the collector.
• For this to happen the base needs to be very narrow (the
neutral length of the base needs to be much smaller than the
electron diffusion length).
• The current through the emitter base should be compose almost
entirely of electrons injected from the emitter rather than
holes from the base to the emitter.
• This can be achieved by heavily doping the emitter and only
lightly doping the base.
e-
N+
Emitter
P
Base
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N
Collector
MOS Transistor
•
•
•
•
The three components are the Source (S), Gate (G) and Drain(D)
Gate is TOTALLY insulated from Semiconductor
Current will be Minority Carriers of substrate under Gate!
Quiescent State: Gate is reverse voltage of substrate (- for ptype and + for n-type.) This repels/depletes silicon below gate
(between S and D) of any minority carriers.
• Conducting State: Gate is same as substrate (+ for p-type and –
for n-type substrate).
o Gate pulls minority carriers from substrate to thin layer
(5nm) connecting Source and Drain with their majority
carriers.
o Forward bias of Source/Gate injects majority carriers into
thin layer.
o Bias of Gate/Drain creates field that pulls majority carriers
into Drain.
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Biasing of a MOS Transistor
This positive charge attracts
With
thethe
switch
open
there isano
When
switch
is closed,
out
the intrinsic
negative
potential
applied
the
gate.
positive
voltageinto
isthe
applied
charge
carriers
bulk to the
There
no conduction path
gate. isThis
silicon.
forms a channel of
between the source and drain
continuous charge allowing
and so no current flows
current to flow between the
source and drain
+
0.7 volts
Vgs
++++ ++++
N+
-----------P
-
3 volts
Vds
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N+
• The MOS transistor is therefore just a switch.
• No current ever flows from the gate to the substrate under any
bias.
• The gate has to be totally insulated from the source, drain and
substrate.
• A small voltage applied to the gate determines whether current
flows between the source and drain.
• A very small change in the gate source voltage can yield a
substantial change in the drain source current that flows.
• While there is an initial linear increase in drain/source current
with drain/source voltage, this does level off into saturation
mode.
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Example of Characteristics Curves of an Nchannel MOSFET
600
Linear Region
Saturation Region
VGS = +5V
Drain Current, IDS (ma)
500
VGS = +4V
400
300
VGS = +3V
200
VGS = +2V
100
VGS = +1V
0
0
1
2
3
4
Drain-Source Voltage, VDS (volts)
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5
6
Calculation of Ids
• The whole idea of a MOS transistor is to use a voltage on the
gate to induce a charge into the channel region between the
source and drain so that current can flow under the influence of
the electric field created by the voltage applied between the
two.
• Since the charge induced depends on the voltage applied to the
gate Vgs, then the current between the source and drain Ids will
depend Vgs and the voltage applied between the source an drain,
Vds.
I ds 
Charge induced in the channel (Qc )
Electron Transit Time ( )
• The transit time is given as:
 sd 
Length of the channel ( L)
Velocity (v)
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• The velocity is then defined as:
v  m Eds
where μ is the electron/hole mobility
and Eds is the electric field applied across the source and drain
• The electric field is given as the voltage over the channel
length,
Vds
Eds 
L
• All this can be used to define the transit time in the source
drain region,
L2
 sd 
m Vds
• As stated before charge is induced in the channel due to gate
voltage Vgs
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• The voltage drop along the channel though is linear with distance
x from the source (due to the IR drop in the channel). Assuming
then that the device is unsaturated, the average voltage drop
along the channel will be,
Vds
2
• Since there is a threshold voltage (Vt) required to invert the
charge under the gate, this means that the effective gate
voltage is,
Vg  Vgs  Vt
• Given that charge per unit area is Eg εins εo
• The induced charge in the channel is then,
Qc  E g  ins  0 W L
where Eg is the average E field gate to channel, εins is the
relative permittivity of the gate insulator, εo is the
permittivity of free space, W is the width of the gate
and L is the length of the channel
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• The average electric field Eg (from the gate to the channel) can
be defined in terms of the voltage drop across the insulating
oxide and its thickness;
 Vg  average channel voltage 

Eg  
d


V 

 Vgs  Vt   ds 
2 
Eg  
d






• So the induced charge can be defined as,
Qc 
W L  ins  0 
Vds 


V

V

 gs t

d
2


• and the drain source current therefore defined as,
I ds 
 ins  0 m W 
d
V 
 Vgs  Vt  ds Vds
L
2 
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• This equation can also be written as
W
I ds  K
L
where
K
2

V ds 
 Vgs  Vt Vds 


2 

 ins  0 m
d
 m Cox
Cox is the capacitance per
unit area of the oxide
• Saturation begins when Vds = Vgs – Vt since the IR drop in the
channel now equals the effective gate to channel voltage at the
drain and the current remains fairly constant as Vds increases
further. Therefore,
W
I ds  K
L
 Vgs  Vt 2 




2


• These expressions of current are valid for both depletion and
enhancement mode devices.
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Enhancement and Depletion Mode
• Since the MOS transistor is just a switch it can be designed to
be continuously on in standby mode or continuously off.
• These conditions are defined as enhancement and depletion
mode transistors.
MOS
Type
n-MOS
Mode
depletion
Standby
Condition
On
Vgs
switching
-
Structure
Gate
Source
N+
n-MOS
enhancement Off
+
Gate
Source
N+
p-MOS
depletion
On
+
enhancement Off
-
Source
N
Drain
P+
Gate
Source
P+
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P
Drain
N+
Gate
P+
p-MOS
P
Drain
N+
N
Drain
P+
Inverters
• The most basic part of any integrated circuit is the inverter,
which gives the ability to change a “on” signal into an “off” signal.
NMOS Depletion
(on in standby)
Input
Output
Hi
Lo
Lo
Hi
5V
5V In
0V
Out
0V
The
transistor
The
Nowdepletion
circuit
the depletion
could
also
mode
be
switches
off
while
produced
transistor
using
switches
twothe
pmos
on while
enhancement
one switches
transistors,
the enhancement
again
mode
one oneon.
This
results
inand
a “Lo”
enhancement
switches
off,
yielding
oneoutput
depletion
a “Hi”
NMOS Enhancement output
(off in standby)
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CMOS – Complimentary Metal Oxide Silicon
• Originally pmos technology only was used for integrated circuits,
this changed in the mid seventies when it became apparent that
nmos technology was required for speed.
• In 1974 the 8080 was produced using nmos technology only.
• Late into the 1970’s nmos technology started to suffer from
power consumption problems and so CMOS has become the
technology of choice since the early 80’s.
• This involves using both nmos and pmos transistors to produce
inverters (the basic building block of any IC)
• The CMOS advantage is that the output of a CMOS inverter can
be as high as the power supply voltage and as low as ground. This
large voltage swing and the steep transition between logic levels
yield large operation margins and therefore also a high circuit
yield.
• In addition, there is no power dissipation in either logic state.
Instead the power dissipation occurs only when a transition is
made between logic states.
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CMOS Inverter
• The CMOS inverter is produced using a single pmos and a single
nmos transistor.
• The big advantage of this circuit is that neither transistor is in
a constant “on” state and so power dissipation is much less than
using only NMOS or only PMOS transistors
PMOS Transistor
Input
Output
Hi
Lo
Lo
Hi
5V
In
Out
A negative
orinput
Lo input,
switches
A positive
causes
the
theNMOS
NMOStransistor
transistortooff
switch on.
0V
NMOS Transistor
The PMOS
one remains
offon
A PMOS
transistor,
switches
resulting
a “Lo”
output
resulting
in ain“Hi”
output.
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SRAM Cell
• The SRAM cell is a six transistor unit that is used extensively in
CPU design.
Word Line
+V
To write
read the
To
a 1 to the
contents
of the
cell,
Bit1 Line
is cell,
the twotobit
forces
0 lines are
pre-charged
high. to
This
force a zero
the
theis2nd
Thegate
wordofline
PMOS
then enabled
Bit1 Line
Bit2 Line
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This
forces
If a in
1 isturns
stored
in
1 Line
the
thiswill
the output
cell Bitof
inverter
to high
be discharged.
latching a 1 into the
If a of
0 is
stored
gate
the
first2 in
the cell the Bit
inverter
Line will be
discharged
Parasitic Capacitances
• A problem with all pn junction transistors is the inherent
parasitic capacitances that are created.
• These capacitances both slow down the device and can cause
latch-up, a condition which gives rise to the establishment of low
resistance conductance paths between the source and drain.
Gate
Source
Drain
N+
N+
P
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• Everywhere there
is a pn junction, a
diode is formed. A
depletion region
(and hence a
capacitance) exists.
• The gate oxide
itself also forms a
capacitor, not only
with the substrate
but also the source
and drain.
Latch-Up
• While CMOS cell have many advantages over NMOS or PMOS
transistors alone, they do suffer with one major issue ……..
Latch-Up !!!
• This is a condition which designers are very aware of as it can
cause a functioning part to fail completely.
• As shown on the previous slide, diode are formed anywhere
there is p-type material in contact with n-type material.
• In a CMOS device it is possible to unintentionally have PNP and
NPN transistors form and provide paths of lower resistance
resulting in constantly on transistors which burn-out.
• Latchup may be induced by glitches in the power supply rail or
even by incident radiation
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Latch-Up Formation
• The substrate which is N-well is connected via an N+ diffusion
tap to Vcc while the P-well is terminated at ground.
• There are effectively two transistors and resistors forming a
path between Vcc and Ground.
• If sufficient substrate current flows such that the voltage
across R1 can turn on T1, this will then draw current through R2
which can generate sufficient voltage to turn on T2.
Vin
Gnd
P+
T2
Vcc
Vout
N+
N+
P+
R2
P+
T1
P- Well
R1
N - Well
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N+