Transcript No Slide Title - CSE, IIT Bombay

Technology CAD: Technology
Modeling, Device Design and
Simulation
S. Saha and B. Gadepally
2004 VLSI Design Tutorial, January 5, 2004
Mumbai, India
S. Saha and B. Gadepally
Technology CAD: Technology
Modeling, Device Design and
Simulation
Coordinator: Prof. Bhaskar Gadepally
Adjunct Prof., Electrical Engineering, IIT Bombay
Chairman, Reliance Software Consulting, Inc.
155 E. Campbell Ave., Campbell, CA 95008 (USA)
[email protected]
2004 VLSI Design Tutorial, January 5, 2004
Mumbai, India
S. Saha and B. Gadepally
Technology CAD: Technology
Modeling, Device Design and
Simulation
Instructor: Dr. Samar Saha
Silicon Storage Technology, Inc.
1171 Sonora Court
Sunnyvale, CA 94086 (USA)
[email protected]
2004 VLSI Design Tutorial, January 5, 2004
Mumbai, India
S. Saha and B. Gadepally
Tutorial Outline
• Prof. B. Gadepally:
– Introduction and Tutorial Overview.
• Dr. S. Saha:
– Front-end Process Technology CAD (TCAD) Models and
Process Simulations
– Device TCAD Models and Device Simulations
– Industrial Application of TCAD
 Calibration of Process and Device Models
– Industrial Application of TCAD in
 Device Research
 Compact / SPICE Modeling.
Mumbai, India
S. Saha and B. Gadepally
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Technology CAD: Technology Modeling,
Device Design and Simulation
Introduction and Tutorial Overview
2004 VLSI Design Tutorial, January 5, 2004
Mumbai, India
Bhaskar Gadepally
Overview of IC Technology
• In the past three decades:
– device densities have grown exponentially
– device and technology complexities have increased
significantly
– design constraints are many-fold:
 ultra thin oxide
 interconnect
 power supply
– technology development cost has increased enormously.
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Overview of IC Technology
Gate Engineering: Dielectric
- ultra-thin gate oxide
- direct tunneling
- high-k dielectrics
Gate Engineering: Stack
- dual-poly / poly depletion
- work function engineering
- interface properties
N+ poly
P+ poly
Spacer
n+
n+
p-well
STI
p+
n-well
NMOS
PMOS
p-substrate
Channel Engineering
- non-uniform channel doping
- Quantum Mechanical effects
- low-diffusivity impurities
- threshold voltage control
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Halo
p+
STI
(Shallow
Trench
Isolation)
Source-Drain Engineering
- ultra-shallow extensions
- low-energy implants
- RTA/LTA techniques
- halo optimization
Bhaskar Gadepally
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Overview of IC Devices
• New device and device physics are continuously
evolving:
– nano-scale devices
– microscopic diffusion
– quantum mechanical carrier transport
– molecular dynamics
– quantum chemistry
– high-frequency interconnect behavior.
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Technology CAD
• With the increased complexities in IC process and
device physics:
– intuitive analysis is no longer possible to design
advanced IC processes and devices
– TCAD tools are crucial for efficient technology and
device design
 to quantify potential roadblocks
 to indicate new solutions
 for continuos scaling of devices.
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Technology CAD
• Scope of TCAD:
– front-end process modeling and simulation
 implant, diffusion, oxidation etc.
– numerical device modeling and simulation
 I - V, C - V etc. simulation
– topography modeling and simulation
 deposition, lithography, etching etc.
– device modeling for circuit simulation
 compact / SPICE modeling
– interconnect simulation
 capacitance, inductance etc.
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Tutorial Objective
• Offer insight into the physical basis of TCAD,
especially, bulk-process and device TCAD.
• Describe systematic methodologies for an effective
application of TCAD tools.
• Describe systematic calibration methodology for
predictive usage of TCAD tools:
– process models
– device models.
• Offer users sufficient insight to leverage new tools.
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Session 1: Bulk-Process Simulation
• Front-end process models implemented in process
TCAD tools:
– ion implantation models
 analytical
 Monte Carlo
– microscopic diffusion models
 point defects
– oxidation
 transient enhanced diffusion.
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Session 2: Device Simulation
• Device models implemented in device TCAD tools:
– fundamentals of carrier transport
 drift-diffusion solution
 hydrodynamic solution
 carrier mobility models
– device physics of nanoscale technology
 inversion layer quantization
– fundamental limits of MOSFETs.
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Session 3: Industry Application
• Introduction to process and device simulation tools.
• Mesh generation.
• Model selection.
• Predictive usage of TCAD:
– process model calibration
– device model calibration.
• Predictive simulation of CMOS technology.
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Moderate
Low
TD Effectiveness
High
Session 3: Industry Application - Calibration
No or a limited
calibration only
provides some
physical trends
and is useful
for a first-order
process and
device analysis.
Low
Global calibration
provides higher
accuracy and
predictability of
Local calibration simulation data.
with the previous
generation of
technology will
provide physical
trends. Absolute
values may not
match real data.
Moderate
High
Calibration Effort
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Session 4: TCAD in Research & Modeling
• Simulation tools in device research:
– simulation structure
– model selection
– examples
 sub-100 nm MOSFETs
 DG-MOSFETs - FinFETs.
• TCAD in device (compact) modeling:
– examples
 substrate current model
 flash memory cell macro-model.
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Technology CAD: Technology Modeling,
Device Design and Simulation
Bulk-Process Simulation
2004 VLSI Design Tutorial, January 5, 2004
Mumbai, India
Samar Saha
Outline
• Introduction.
• Bulk-process Models:
– Ion Implantation
– Diffusion
– Oxidation.
• Summary.
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Introduction
P+ poly
Spacer
N+ poly
Gate oxide
Source
n+
p-well
Drain
n+
STI
Source
p+
Drain
p+
n-well
NMOS
PMOS
p-substrate
Halo
STI
(Shallow
Trench
Isolation)
• Front-end IC fabrication processes include:
– implant: S/D and halo (low energy); well (high energy) etc.
– diffusion: Rapid thermal annealing (RTA)  Transient
Enhanced Diffusion (TED) and other anomalous effects
– oxidation: gate oxide, STI liner oxide etc.
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Introduction
• Objective of this session:
– understanding of physical models implemented in a
process TCAD tool
 model hierarchy
 model limitations
 building new models
– basic understanding of general purpose simulator
internals
– TCAD models in general without considering any
particular tools.
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Ion Implantation
• Ion Implantation Mechanisms.
• Ion Implant Models:
– Analytical
– Monte Carlo (MC).
• Implant-induced Damage Modeling.
• “Plus-one” Approximation.
• Summary.
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Ion Implantation
• Bombard
wafers
with
energetic ions energy, E
0.5 KeV - 1 MeV > Ebinding.
Ion
Target
– ion deflections, energy loss
– displaced target atoms
(recoils).
Recoil
• Ions collide elastically with
target atoms creating:
• Ions suffer inelastic drag
force from target electrons
– ion energy loss
– lattice heating.
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Ion Implantation
• Ions come to rest after
losing all the energy on:
– elastic collisions (nuclear
stopping)
Ion
Target
Recoil
• Channeling is caused by
ions traveling with few
collisions and little drag
along
certain
crystal
directions.
– inelastic drag (electronic
stopping).
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Ion Energy Loss Mechanisms
• Nuclear stopping (Sn(E)):
q
– ion energy loss to target
atom by interaction with
the electric field of the
Ion
target atom’s nucleus
– classical relationship of two colliding particles
– the scattering potential with the exponential screening
function is given by
V (r ) 
q 2 Z1 Z2
 ai ebi a
r
4r
where
Z1 = atomic number of incoming ion
Z2 = atomic number of target atom.
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Ion Energy Loss Mechanisms
• Electronic stopping (Se(E)) is due to the viscous drag
force on moving ion in a dielectric medium.
Se  k e Z1 , Z 2 ,... E
– ke is a model parameter.
• Accurate model must
account for the variation
of Se in space.
• Stopping power S of an
ion is given by:
 dE 
 dE 
S 



 dx  nuclear  dx electronic
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Ion Range Distribution
• Ions come to rest over a distribution of locations.
• Peak, depth, and lateral spread of distribution are
determined by:
– ion mass, energy, dose, and incident angle
– target atom, composition, geometry, structure, and
temperature.
• Implanted profile can be represented by:
– particles
– distribution functions.
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Ion Range Distribution
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Ion Range Distribution
• The as-implanted 1D
distribution function is
described by a series
of coefficients called
moments.
• 2D distribution of the
implanted profile is
constructed from 1D
distribution function
taking lateral spread
 vertical spread.
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1D Analytical Ion Implantation Models
• Gaussian distribution:
N
– amorphous targets
– two coefficients
 x  R p 2 
Q
N ( x) 
exp 

2
2 s p 
2 s p

Rp
x
where
Q = implant dose (#/cm-2)
Rp = projected range  normalized first moment
sp = straggle/standard deviation  second moment.
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1D Analytical Ion Implantation Models
• Pearson-IV:
– crystalline targets without channeling
 four coefficients (Rp, sp, skewness, kurtosis)
– crystalline targets with channeling, tilt, and rotation.
 six coefficients.
• Dual Pearson-IV:
– crystalline targets with channeling, tilt, and rotation
– second profile to model the channeling
– nine coefficients.
• Legendre Polynomials - 19 coefficients.
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1D Analytical Ion Implantation Models
• Coefficients are fit to the measured doping profiles.
• Coefficient-set for each distribution is tabulated for
different:
– ion mass (As, B, In, P, Sb)
– dose, energy, tilt, and rotation
– target type.
• Multi-layer targets:
– each material is treated separately and scaled by its Rp.
– dose absorbed on the top layer is calculated and is used
as the dose matching thickness for the layer below.
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2D/3D Analytical Ion Implantation Models
• Each 1D profile along a vertical line is converted to
2D or 3D distribution by multiplying it by a function of
lateral coordinates:
2
 y
exp  
2s l

N ( x, y)  N1 ( x)
2 s l
here lateral straggle, sl  sp



• Multi-layer targets and sloped surfaces are
converted to 2D/3D by dose matching approach.
• More complex models have sl(x).
• Low energy profiles need non-separable pointresponse functions.
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Monte Carlo Modeling of Ion Implantation
• The collision energy loss is modeled by binary
collision approximation (BCA), that is, each ion
collides with one target atom at a time.
• The energy loss (DE) is modeled in terms of:
– incident energy, E0 and scattering angle, q0 of ion
– separation between two particles
– coulomb potential between two particles
– impact parameter.
• BCA requires special formulation for:
– ion channeling
– low energies when lattice movements come into play.
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Monte Carlo Modeling of Ion Implantation
• Ongoing development in MC modeling is to improve:
– speed of calculations
– electronic stopping power, Se model
 detailed local model for Se
 local and non-local split in energy loss due to Se

1  f nl
 p 
DE   f nl NL 
exp     S e
2
2a
 a 

where
fnl = fraction of non-local energy split
a = universal screening length
p = impact parameter.
• Overall accuracy of MC implant model is excellent.
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Ion Channeling in Crystalline Silicon
• Along certain angles in crystal, ion may encounter
no target atoms.
• Repeated small-angle
collisions steer the ion
back into the channel.
Ion
• Channeling was first discovered by MC simulation.
• Channeling is:
– important at any energy
– critical at low energy where <110> channels steer Boron
ions under MOS gate.
• Analytic channeling model is complex.
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Ion Channeling in Crystalline Silicon
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Damage Creation Models
• Each incoming ions generates damage seen by
subsequent ions:
– recoils  target atoms knocked out of lattice sites
– amorphous pockets.
• The effect of damage is significant on as-implanted
profile as well as during subsequent diffusion.
• Models based on Kinchin-Pease formulation is used
to estimate damage density: n = Er/2Ed
where
Er = recoil energy
Ed = target displacement energy (~ 15 eV for Silicon).
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“Plus-one” Damage Model
• Most recoiled interstitials (I) find a vacancy (V) and
recombine rapidly either during the implantation or
the first instants of annealing.
• Distribution of remaining recoils shows:
– net excess of V near the surface
– net excess of I toward bulk.
• At low ion mass and/or moderate energy:
– population of net I and net V is less than the population
of I due to dopant atoms taking substitutional sites
– one “extra-ion” is created for each dopant atom taking a
substitutional site.
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Deviation from “Plus-one” Model
• “Plus-one” approximation often fails for:
– heavy ions
 as the population of recoils can become quite large
relative to extra ion population
– low energy
– low dose.
• An effective “plus-n” factor as a function of ion
species, energy, and dose is used. Typical values:
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As:
n  3.5 @ E  5 KeV; n  1.2 @ E  500 KeV
B:
n  1.2 @ E  5 KeV; n  1.0 for E > 20 KeV
P:
n  2.2 @ E  5 KeV; n  1.0 @ E  500 KeV.
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Ion Implantation: Summary
• Ion implantation with ion energy > Ebinding of target
atoms is used to implant impurity atoms into target.
• Analytical ion implantation model:
– the impurity profile is represented by moments for
different species, dose, energy, tilt, and rotation
– the moments are extracted from the experimental profile
to create look-up table
– simulation is performed using this look-up table.
• MC ion implantation model is more accurate,
particularly for low energy.
• The implant damage is modeled by “plus-n” model.
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Diffusion
• Fundamentals of Dopant Diffusion
– Fick’s Laws
– Oxidation Enhanced Diffusion (OED)
– Oxidation Retarded Diffusion (ORD)
– Transient Enhanced Diffusion (TED).
• Point Defect Model.
• Clusters and Precipitates.
• Polysilicon Diffusion.
• Impurity Profiling.
• Summary.
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Fick’s Laws of Diffusion
• Fick’s first law:
– describes flux (F) through any surface
– diffusion is downhill - high  low concentration, “- sign”
DC
F  D
  DC
(D  diffusivity = constant)
Dx
• Fick’s second law  law of conservation of particles
C
 .F
t
• Low concentration diffusion in
silicon is Fickian - each dopant
A satisfies: C A
 .D 0A A
t
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Fin
DC
Fout
Dx
42
Concentration-Dependent Diffusion
• Typically, intrinsic carrier concentrations (ni) at
processing temperatures are high  1019 cm-3.
• For high doping concentrations, C > ni, dopant
diffusion shows enhancements of the form:
2
n n
 p
D




 

1

a

b

c
0




D
 ni   ni 
 ni 
• Diffusion enhancement is due to the variation of
point defect population with Fermi level.
• The effective extrinsic diffusivity is given by:
2
 p
n
n
D  Dx  D p    Dm    Dmm   ;
 ni 
 ni 
 ni 
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Samar Saha
where
D o  Dx  D p  Dm  Dmm
43
Surface Effects on Bulk Diffusion: OED/ORD
• Experimental data show that processes which
modify the surface can affect diffusion in the bulk.
Species /
defects
B, P, I
As
Sb
Stacking
Faults
Diffusion process
Oxidation Oxinitridation Nitridation
Enhanced
Enhanced
Enhanced
then retarded
Enhanced
Enhanced
Enhanced
then retarded
Retarded
Enhanced
Grow
Grow
Shrink
Enhanced
• Enhancement of diffusivity in one species while
retardation in another is the evidence of two different
diffusion mechanisms  I and V.
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Transient Enhanced Diffusion (TED)
• Anomalous displacement of implanted dopants during
low temperature anneals.
• Reverse temperature effect: displacement larger at
lower temperatures - up to 0.3-0.4 mm.
• Displacement increases with implant dose and energy.
• Corresponds to temporary increase in diffusivity ~
10,000X.
• Implant of one species can drive diffusion of another.
• Enhancement is transient.
• Spatially non-uniform diffusion enhancements.
• Reduced activation.
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Transient Enhanced Diffusion (TED)
• As implanted over a
buried B layer.
• As implant creates
damage deep into
the substrate.
• The implant damage
causes a significant
enhancement in B
diffusion deep into
the substrate during
20 sec. anneal at
850 °C.
Simulation results 
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Point Defect Model for Dopant Diffusion
• Point defects (I and V) model explains:
– most of the observed trends in dopant diffusion by
relating them to the properties of I and V
– “action-at-a-distance” effect of the surface on bulk
diffusion.
Vacancy mechanism
As, Sb
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Kick-out mechanism
B, P, In, As, Au, Zn, P
above 900 °C
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Frank-Turnbull
mechanism
Zn, below 900 °C
47
Defect Charge States
• Defects which have states in the gap will have a
distribution of charge states.
• The concentration of charged point defects depends
on Fermi level.
• Dopants can diffuse with any of the defect charge
states, some combinations have higher probability.
• In principle, must solve a set of: N dopant  N defect N ch arg e 
N dopant N defect N ch arg e PDEs one for each combination.
• “Five-stream” diffusion model solves equations:
N dopant  N defect  N dopant N ch arg e
• “Three-stream” model solves N dopant  N defect equations.
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“Electric-field” Effects
For high doping
concentration > ni
at the processing
temperature, the
electric field set up
by ionized dopants
affects diffusivity.
Example:
As + B co-diffusion
at 900 °C, 15 min.
 B- pulled towards
the N+ region due to
e-field effects.
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Generation/Recombination of Defects
• General flux model: Fsurf  Fgen  Frec
g
G
where Fgen  qVmG  , q = fraction of silicon atom injected
 G0 
  G k 
Frec  K inert  K r    1 ( I  I * )  K total ( I  I * ).
  G0 

– Vm = silicon atom/cm3
– assumed generation  growth rate, G.
– recombination rate  surface excess I - I* and increases
under a growing surface.
• Lateral diffusion of defects during OED is governed
by the ratio of DI/Kinert  10 mm.
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Surface Generation/Recombination
• During OED, recombination/generation fluxes are
large and must balance:
Fgen
*
I  I 
K total
• Fixed interstitial super-saturations, also, occur under
nitride, silicide surfaces.
• During TED, recombination appears to be fast, even
at inert surfaces, recombination rate: DI Kinert  0.1mm.
• Several models are available.
• Optimize Kinert for TED and adjust q to fit OED at the
expense of lateral OED decay length.
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Gradient Effects in Transient Diffusion
• Dopant flux arises from diffusion of defects-dopant
pairs:
boron flux = DBI[BI].
• Number of pairs is proportional to the boron and
interstitial concentrations:
boron flux = DBIkpair(IB + BI)
where
IB = interstitials enhance boron diffusion
I = boron diffusion due to defect gradient
• During TED, I is large near the surface causing:
– extra dopant flux to the surface
– surface pile-up (and possible interface loss) of dopant.
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52
Interstitial Clustering Model
• The growth and dissolution is given by:
C
  k d C  k c CI
t
where
kd is the decay constant
kc is the growth constant
C = concentration of clustered interstitials
I = concentration of unclustered interstitials.
• After implantation I is large, dC/dt = C(kcI)  clusters
grow exponentially until I = kd/kc.
• When I is small, clusters decay exponentially with
time constant 1/kd.
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{311} Cluster Dissolution
• {311} defects:
– rod-shaped defect clusters condensed from “+1” amount
of damaged silicon-I at annealing T > 400 °C
– precipitate on {311} planes and extend in the <110>
directions to form planar defects.
• Time scale for {311} evaporation is similar to the time
scale for TED.
• Simple reaction-based model
account of evaporation curve.
offers
first-order
• Steady super saturation of dopant diffusion is
observed during TED.
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54
Dopant Clustering/Precipitation
• Dopants are only soluble up to a limit at any
temperature (solid solubility limit).
• Dopants also show deactivation below the solid
solubility limit.
• Due to the clusters of size
m dopant atoms such as
As with m = 4,
– clustering reaction emits
interstitials to generate required V.
As
V
As
As
As
 Can generate enhanced diffusion at the same level
as TED.
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55
Chemical Pump Effects
• Dopant atom A interacting with I form A + I  AI
interstitial-assisted mobile species.
• When AI pairs diffuse out of a region of high I* to a
region of low I*, pairs are out of equilibrium and must
dissociate, AI  A + I.
• A is deposited while I diffuses (“pumped”) away from
the surface enhancing diffusion in bulk.
• Surface dopant layer may cause enhanced diffusion
in bulk - e.g. D/D* = 70 at 900 °C.
• Causes cooperative diffusion, e.g. emitter push
effect in bipolar junction transistors.
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56
Diffusion in Polysilicon
• Point defects usually pinned near equilibrium in poly
due to grain boundaries.
• Dopants diffuse in two streams via grain and in
boundary.
• An effective model includes:
– two streams
– dopant transfer from grain to grain boundary
– grain growth with time
– dopant transfer to grain boundary.
• Segregation coefficient, growth rate, and re-growth
rate = f(temperature, grain size, Fermi level).
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57
Metrology for Developing Diffusion Models
– 1D carrier
profiles
– good sensitivity
– modest depth
resolution
– carrier spilling
– difficult to use
for shallow
junctions.
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Log(Concentration (cm-3))
• Spreading resistance
profile (SRP)
1.E+21
n
1.E+20
1.E+19
1.E+18
1.E+17
p
1.E+16
1.E+15
0.0
Samar Saha
0.2
0.4 0.6 0.8
Depth (mm)
1.0
1.2
58
Metrology for Developing Diffusion Models
• Secondary Ion Mass Spectroscopy (SIMS)
– 1D chemical profiles
– good sensitivity to all dopants
– excellent depth resolution
– surface region troublesome.
• 2D carrier profiling with excellent space resolution:
– scanning capacitance microscopy (SCM)
 measurement affects sample
– transmission electron holography (TEH)
 measures electrostatic potential
 difficult sample preparation.
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59
Monte Carlo Diffusion Methods: Algorithm
Monte Carlo diffusion program (MARLOWE, UT-Austin) offers
accurate diffusion modeling.
MARLOWE
Generates initial I, V positions
THEORETICAL
CALCULATIONS
Energy of interactions
and
diffusion barriers
EXPERIMENTS
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MONTE CARLO DIFFUSION CODE
- Diffusion
- Clustering
- I - V recombination
- Surface annihilation
- I, V trapping
- Boron kick-out, kick-in
Samar Saha
60
Diffusion: Summary
• Diffusion is critical to activate the implanted dopants
in the semiconductor devices.
• Dopants diffuse in silicon by interacting with point
defects through a number of possible atomic-scale
mechanisms.
• For short times, the diffusion is dominated by TED
because of high concentration of point defects.
• Point defect concentrations depend on temperature,
Fermi level, implant damage, and surface processes
like oxidation.
• 1D/2D metrology is used to calibrate diffusion model.
Mumbai, India
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61
Oxidation
• Fundamentals of Thermal Oxidation.
• Oxide Growth Model:
– Deal-Grove Model
– Thin Oxide Model.
• Oxidation Chemistry.
• Oxide Flow:
– Oxidation-induced Stress
– Visco-elastic Model.
• Summary.
Mumbai, India
Samar Saha
62
Oxidation: Diffusion, Reaction, Flow
• Oxidation proceeds by three sequential processes:
– oxidant diffuses through existing oxide
– oxidant reacts at silicon surface to create new oxide
– overlying oxide flows to accommodate new volume.
O2 or H2O ambient
Nitride
Oxidant
Reaction
zone
Silicon
• Process is at first limited by reaction but diffusion
through growing oxide becomes limiting.
Mumbai, India
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63
Oxidation: Deal-Grove Model
C0
Fdiff   D
CL  C0 
L
Freac = kCL
CL
SiO2
Silicon
D = diffusivity of oxidant
CL = concentration at Si-SiO2 interface
C0 = concentration at the SiO2 surface
L = oxide thickness
k = interface reaction rate constant
Mumbai, India
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64
Oxidation: Deal-Grove Model
C0
Fdiff   D
CL  C0 
L
Freac = kCL
CL
SiO2
Silicon
• At equilibrium: Fdiff = Freac,  CL = C0 / [1 + kL/D]
• Oxidation growth rate is given by: L 
t
where
B  2C * D N s ; B A  k C * N s
1
1
2L

B A B
C* = equil. oxidant conc.; Ns = # oxidant/cm3 in oxide
Mumbai, India
Samar Saha
65
Thin Oxide Models
• Deal-Grove model does not fit the early part of
oxidation curve.
• The data in thin regime can be fitted with an addition
to Deal-Grove model given by:
L
1
 L

 C exp   
1
2L
t
 l

B A B
 E 
C  C 0 exp   A  and
 kT 
C0  3.6x108 mm/hr, EA  2.35 eV, and l  7 nm in <111>
or <100> oriented silicon substrates.
where
• This model can be found in TCAD tools like SUPREM4.
Mumbai, India
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66
Oxidation - Planar Growth
• Planar growth generates an intrinsic stress in oxide
during growth process:
– modest stress (3x109 dynes/cm2)
– density increases (< 3%)
– refractive index increases (1%) relative to fully relaxed
oxides.
First oxidation
• Two-step oxidation
shows a significant
difference in oxide
density.
1100 C
800 C
Second oxidation
900 C
900 C
DL grown in the second step varies depending on the
thermal history of oxide (not just on L).
Mumbai, India
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67
Oxidation - Planar Growth
• Intrinsic stress is an atomistic process.
• Relaxes gradually with annealing at a rate which
steadily decreases.
• Recent measurements show that relaxation rate is
independent of stress level.
• History effects are not accounted for in most process
simulators.
• Measured linear/parabolic coefficients
oxidation in a state of intrinsic stress.
describe
 1D stress already accounted for in one-step
oxidation.
Mumbai, India
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68
Oxidation Chemistry
• Oxidation rate coefficients are sensitive to ambient
additives:
– steam 20 - 50 times faster than O2
– 3% Cl2 increases growth rate by 20 - 30%
– 100 ppm NF2 increases growth rate by 2 - 5
– heavy substrate doping increases rate by 2 - 10
according to the relation
n
k
n
p
 a  b  c  d  
k0
ni
ni
 ni 
2
– all easily accounted for by building table of B, B/A vs.
additive or dopant concentration.
– NO, NO2 are not supported in most process TCAD tools.
Mumbai, India
Samar Saha
69
Oxide Flow
• Oxide growing on a curved
surface must flow.
Old Oxide
Silicon
New Oxide
• Resulting deformations (and stresses) can be large!
LOCOS top surface must stretch by 15 - 20%.
Si3N4
Oxide
Silicon
• Elastic limit of glass << 1%
Mumbai, India
Samar Saha
70
Oxide Flow
• Large deformations on a curved surface during
oxidation mean viscous flow must occur.
• Viscous flow model used to model stress during
oxide growth includes:
– incompressible viscous flow
– linear elasticity.
• Visco-elastic flow model:
– allows oxide to be “slightly” compressible
– eliminates pressure equation
– offers a significant numerical benefit.
Mumbai, India
Samar Saha
71
Visco-elastic Model: Stress Simulation
• Oxide stress
after
local
oxidation.
Si3N4
• Length
of
stress vector
 amount of
stress.
SiO2
Compression
Tension
Mumbai, India
Samar Saha
72
Oxidation: Summary
• Basic growth mechanism of thermal oxide:
– oxidant transport through the SiO2 layer to Si/SiO2
interface
– chemical reaction at the interface to produce the new
layer of oxide.
• The growth is linear parabolic law.
• The basic Deal-Grove model is extended to explain:
– thin oxide growth
– mixed ambient oxidation.
• Important effects of thermal oxidation include OED,
ORD, and impurity redistribution and segregation.
Mumbai, India
Samar Saha
73
Bulk-Process Simulation: Summary
• Accurate process models and TCAD tools are
extremely critical for continuous scaling of IC’s .
• Workstation performance is continuously improving
for cost-effective computer experiments.
• Existing models and TCAD tools treat different
aspects of process simulation quite well.
• As new understanding develops, new models are
incorporated in TCAD tools to improve predictability.
• Successful process TCAD will require a firm grasp of
the controlling process physics.
Mumbai, India
Samar Saha
74
Technology CAD: Technology Modeling,
Device Design and Simulation
Device Simulation
2004 VLSI Design Tutorial, January 5, 2004
Mumbai, India
Samar Saha
Outline
• Introduction.
• Carrier Transport Models.
• Inversion Layer Mobility.
• Quantum Mechanical Confinement.
• Discrete Dopant Effects.
• Numerical Methods.
• Summary.
Mumbai, India
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76
Introduction
• A device TCAD tool solves a set of equations to deal with
various physical phenomena in semiconductor devices:
QM tunneling
Poly
n+
n+
STI
Atomic
scale
effects
STI
Electrostatics:
- 2D/3D effects
- discrete charges
p-well
p-substrate
hot carriers
QM confinement
Non-local transport
(velocity overshoot)
Surface scattering
Quasi-ballistic transport
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77
Introduction
• Objectives of this session is to:
– focus on the underlying physics and models for practical
application of device TCAD such as
 identify device physics issues for simulation
 discuss and compare simulation approaches
 identify
 limitations
 uncertainties
 challenges.
Mumbai, India
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78
Carrier Transport Models
• A device TCAD tool generates device characteristics
by solving:
– Poisson’s [.D = r(r)] + carrier transport equations selfconsistently.
• Carrier transport models include:
– drift-diffusion (DD) - standard
– Monte Carlo (MC)
– molecular dynamics
– hydrodynamic (HD)
– Boltzmann equation
– quantum balance equations.
Mumbai, India
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79
Carrier Transport Models
• The basic concept in transport theory is the carrier
distribution function = f(r,px,t).
• f(r,px,t) = probability of a carrier at the position r with
momentum px at any instant t.
• f(r,px,t) is a Maxwellian
distribution function with:
f(r,px,t)
– area = carrier density, n(r,t)
– the spread depends on
carrier temperature
– first moment is velocity
Equilibrium
px
– second moment is kinetic energy.
Mumbai, India
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80
Carrier Transport Models
f(r,px,t)
Equilibrium
f(r,px,t)
px
Non-equilibrium
x
px
• At equilibrium, f(r,px,t) is symmetric around px = 0.
• If an e-field is applied along the negative px direction:
– electron distribution is distorted and displaced from the
origin
– causes electron scattering.
• Device TCAD challenge is to solve f(r,px,t).
Mumbai, India
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81
Carrier Transport Models
• To solve for f(r,p,t) - Boltzmann Transport Equation
(BTE):
– six dimensions
 three in position space
 three in momentum space
– solution techniques:
 MC simulation
 spherical harmonics
 scattering matrix
 and so on.
Mumbai, India
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82
Carrier Transport Models
• Solving f(r,p,t), we can find the quantities that device
engineers deal with directly such as:
– carrier density, n(r,t)
– current density, Jn(r,t)
– energy current, JE(r,t)
– average kinetic energy, un(r,t)
– electron temperature, Tn(r,t)
– heat flux, Qn(r,t).
• Six-dimensional equation is difficult to solve and
computationally demanding.
 In TCAD, we directly solve for the quantities of interest.
Mumbai, India
Samar Saha
83
Carrier Transport: Balance Equations
• Basic idea to solve for a quantity (nf) of interest is to
formulate a balance equation such as:
– rate of increase in nf = rate nf flows into the volume + net
generation rate.
   Ff
nf
t
   Ff  Gf  Rf
Examples:
Rf
Gf
nf
Mumbai, India
– nf = n(x,t):  continuity
equation.
– nf = Jnx(x,t):  current
equation.
Samar Saha
84
Carrier Transport Models
• Assuming slowly varying time, we can write the
current equation:
 2nu xx / q 
J nx  qnm n x  m n
x
where
mn [ f (r, p, t )]  q t / m *
t = average time between collisions
m* = effective mass of electrons.
• We need a balance equation for kinetic energy, uxx.
• For simplicity of computation:
– approximate the effects of scattering in mn
– close the balance equations by approximating uxx.
Mumbai, India
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85
Carrier Transport Models: Drift-Diffusion
• The simplest solution of carrier transport equation is
local field or DD approach.
• In DD, m is determined by scattering, scattering is
determined by uxx, and uxx is determined by .
• For high fields in bulk silicon, (x) and uxx are
constants or slowly varying:
here mn = m0[N,TL,(x)]; Dn = (kBTL/q)mn
• Then the current equation is given by:
dn
J nx  x, t   qn x, t m n   x ( x)  k BTL m n  
dx
 Local field transport model: [mn = f(local field)]
Mumbai, India
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86
Carrier Transport Models: Drift-Diffusion
• DD solution fails to predict device characteristics for
small geometry ( 0.1 mm) MOSFETs.
• We know:
mn [ f (r, p, t )]  q t / m *
here <t> is related to the average carrier energy,
un(Tn) and Tn = local electron temperature.
• Thus, the DD-transport model can be improved by
assuming, mn as a function of local energy.
Local energy transport model: mn = f(local energy)
Alternatively, mn = m0[N,TL,Tn]
Mumbai, India
Samar Saha
87
Carrier Transport Models: Local Energy
• Solve for energy density, nf = W(x,t) = nu:
dJ Ex  x, t 
n(u  u0 )
 J nx x ( x) 
dx
tE
increase in
energy flux
input e-field
rate of energy
dissipation
where tE = relaxation time.
• nf = JE(x,t):
d ( Dn n) 

J Ex  x, t   C E k BTe nm n x ( x)  q
dx 

• Unknowns: (x), n(x), p(x), un(x), and up(x)
Mumbai, India
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88
Carrier Transport Models: DD vs. HD
DD vs. HD model data deviate significantly for 40 nm devices.
Mumbai, India
Samar Saha
89
Macroscopic Transport Models: Summary
• Models are derived directly from BTE.
• Require numerous simplifying assumptions: closure,
scattering.
• Difficult to assess the validity of assumptions.
• Many flavors: HD, energy transport (ET).
• Beyond DD, adds significant numerical complexity.
• HD/ET generally provide good estimates of:
– average carrier energy
– current density.
• Significant differences between various models.
Mumbai, India
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90
Carrier Transport Models: MC Simulation
• MC is a rigorous transport model.
• The essence of the model is:
dp
  q
r1: free flight duration
dt
r
2
r 3, r 4
r2: scattering event
r3: direction after scattering r4
r1
r1
electron
r2
r 3, r 4
r1
Mumbai, India
Samar Saha
91
MC Simulation: Summary
• Advantages:
– numerical method for solving the BTE with e-e
correlation
– advanced physics is readily treated (e.g. scattering and
complete band structures)
– most reliable transport method for treating hot electron
distributions and for assessing novel devices.
• Disadvantage:
– computationally demanding:
 under near-equilibrium conditions
 for examining rare events.
Mumbai, India
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92
Carrier Transport Models: Quantum
• Different techniques available include:
(1) equilibrium or ballistic transport


 2  EC (r )  E
2m *
 simplest form is used for MOS capacitor simulation
(2) wave propagation with phase randomizing scattering
 non equilibrium Green’s function approach (Wigner
functions, density matrix)
(3) density gradient/QM potential approach
  2 mn    2 n 


J n  nqm nV  qDnn  
*  

 6qmn   n 
Mumbai, India
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93
Carrier Transport Models: Summary
• Drift-diffusion (local field model):
 m = f(local field)
• Balance equations (mostly local energy):
 m = f(local energy)
Examples: HD, ET, etc.
• Boltzmann solvers:
– MC
• Quantum transport:
– Schrodinger-Poisson
– density gradient / quantum potential.
Mumbai, India
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94
Inversion Layer Mobility
• Choice of mobility model
can significantly alter the
simulation results.
• Inversion layer mobility
versus effective normal
electric field show wellknown characteristics:
– high fields: universal
behavior independent of
doping density.
– low fields: dependent
on 1) doping density
and 2) interface charge.
Mumbai, India
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95
Inversion Layer Mobility
• Mobility versus effective normal electric field curve is
modeled using three components:
– coulomb scattering (due to ionized impurity)
– phonon scattering - almost constant
– surface roughness scattering (at Si/SiO2 interface).
• At low normal fields:
– less inversion charge density
– ionized impurity scattering dominates and meff = f(NA).
• At high normal fields:
– higher inversion charge density close to the interface
– surface roughness scattering dominates.
Mumbai, India
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96
Inversion Layer Mobility
• For higher normal fields, universal behavior as a
function of effective normal field:
 eff
q
0.5N S  N depl 

K Si
• The effective field is a non-local quantity.
• Local field mobility models preferred for device
TCAD should produce universal behavior in terms of
the computed effective field.
– Example:
 Lombardi Surface Mobility Model.
Mumbai, India
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97
Inversion Layer Mobility
• For ultra-thin gate oxide thickness the inversion layer
carrier wave function can extend through Si/SiO2
interface to SiO2/polysilicon interface.
Poly
n+
p-well
Gate Oxide
n+
STI
STI
Electron
wave function
NMOS
p-substrate
• Mobility may depend on the surface roughness of
SiO2/polysilicon
interface
“remote
interface
roughness” scattering.
Mumbai, India
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98
Choice of Surface Mobility Models
Mumbai, India
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99
Inversion Layer Mobility: Summary
• Mobility is extremely critical for advanced MOSFET
device simulation.
• Choice of mobility model can effect simulation data.
• Local field mobility models are being extended for
high normal fields and high doping densities.
• New effects may begin to be felt in ultra-thin oxide
devices
– Example:
 remote interface scattering.
Mumbai, India
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100
Quantum Mechanical Confinement
• The charges near the silicon surface are confined to
a potential well formed by:
– oxide barrier
Energy
EC(y)
– bend Si-conduction
band due to applied
gate potential.
• Due to QM confinement of
charges near the surface:
EF
Depth into Si (y)
– energy levels are grouped in discrete energy sub-bands
– each sub-band corresponds to a quantized level for
carrier motion in the normal direction.
Mumbai, India
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101
Quantum Mechanical Confinement
• Due to QM confinement, the inversion layer
concentration:
– peaks below the SiO2/Si interface
  0 at the interface and is determined by the boundary
condition for the electron wave function.
n(y)
Classical
Dz
Quantum
Dz = shift in the centroid of
charge in silicon away from
the interface.
Equivalent oxide thickness for
Dz is:
DTOX (QM ) 
Depth into Si (y)
Mumbai, India
Samar Saha


OX
Dz
Si
102
Quantum Mechanical Confinement
• Classical:
Vgate
– CSi >> COX (accumulation / inversion)
– Ctotal ~ COX (accumulation / inversion)
• Quantum:
Cox
CSi
– CSi ~ Si/Dz
– Ctotal < COX (accumulation / inversion)
• Impact of QM confinement:
– Vth since more band bending is required to populate the
lowest sub-band
– TOXeff since a higher VG over-drive is required to produce a
given level of inversion charge density
– Ctotal since TOXeff = TOX + (OX/Si)Dz.
Mumbai, India
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103
QM Confinement: Modeling Approach
• van Dort’s model: amount of band-gap widening due
to splitting of energy levels is given by:
1
3
2
  semi 
DEg ( y)  B
 En 3 F y / yref 
 4kT 
where
B = constant
y = distance from Si/SiO2 interface
yref = reference distance for the material
En = normal electrical field
and,
Mumbai, India
CL
ni  nCL
(
1

F
(
y
))

ni e
i
Samar Saha

DEg
2 kT
F ( y)
104
QM Confinement: Modeling Approach
• Modified local density approximation (MLDA):
– robust and efficient formulation to compute quantization
of carrier concentration near Si/SiO2 interface
– offers a good compromise between the accuracy and
simulation time
– the confined carrier density is given by FD statistics



 2 
nQM ( y )  N C 
1  j0 (2 y  ln
  d
   0 1  exp   EF kT 
and,

 nQM ( y ) 
E g ( y )   Ec ( y )  EF ( y )   kTF 

N
(
y
)
 c

1
12
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105
QM Confinement: COX Reduction
Simulation data obtained by simulation program TSUPREM4
Mumbai, India
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106
QM Confinement: TOX Measurement
DTOX  TOXeff - TOX
D T OX/T OX (%)
8
7
6
5
4
2
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3
4
T OX (nm)
Samar Saha
5
6
107
QM Confinement: Effect on Vth
1E18
GR
0.08
1e18
uniform
1e17
0.06
0.04
1E17
ST
AR
nMOSFETs
Leff = 100 nm; Tox = 3 nm
VDS = 50 mV; VBS = 0
0.02
5
10
15
20
25
Transition Depth (nm)
1E18
30
GR-Graded
Retrograde
1E17
AR-Abrupt
Retrograde
1E18
Conventional
Step, ST
1E17
0.00
0
Nch (cm-3)
Vth(QM) - Vth(CL) (V)
0.10
Transition
depth
Depth
• Vth increase due to QM effect depends on channel doping, Nch.

Maximum increase in Vth ~ 100 mV for Nch ~ 1x1018 cm-3.
Mumbai, India
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108
D Ion(CL-QM)/Ion(CL) (%)
QM Confinement: Effect on ION
20
1e18
uniform
1e17
15
10
GR
ST
AR
nMOSFETS
Leff = 100 nm; Tox = 3 nm
5
VGS = VDS = 1.5 V; VBS = 0
0
0
5
10
15 20
25
Transition Depth (nm)
30
• Ion decrease due to QM confinement depends on Nch.
• Maximum drop in Ion~ 20% for Nch ~ 1x1018 cm-3.
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109
QM Confinement: Summary
• Impact of QM confinement becomes significant for
TOX < 4 nm.
• QM confinement affects:
– TOX measurement
– drive current
– scaling limits.
• Modeling approaches:
– semi-physical (e.g. van Dort)
– quantum potentials - MLDA
– 1D self-consistent Schrodinger-Poisson.
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110
Discrete Dopant Effects
• The volume of active
channel region for an
advanced MOSFET:
V = (W) x (L) x (Xj)
V
• Typically:
length, L = 40 nm
Xj
P (NA cm-3)
width, W = 100 nm;
junction depth, Xj = 25 nm;
Nchannel = 1x1018 cm-3
 Ntot = 100 impurity atoms.
 The number of dopants in V is a statistical quantity.
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111
Discrete Dopant Effects
• Effects of discrete dopants:


 
  
 
       
 
     

  
   
 
 

– significant threshold (Vth)
variation, sVth (10’s of mV)
– lower average Vth (10’s of
mV)
– asymmetry in drive current,
IDS.
• 3D transport leads to inhomogeneous conduction in
sub-100 nm devices.
• Continuum diffusion models are inadequate to model
discrete dopant effects in sub-100 nm MOSFETs.
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112
Discrete Dopant Effects: Summary
• 2D continuum models can predict spread in Vth.
• Full 3D simulation is necessary to predict mean.
• The role of continuum versus granular models will
become increasingly important as devices continue
to shrink.
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113
Hot Electron Effects
• Effect:
– hot electron injection.
• Outcome:
– substrate current.
• Trends:
– power supplies are decreasing
– electric fields are increasing.
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114
Hot-Carrier Effects
• Channel electron
traveling through
high electric field
near the drain
end can:
Gate
n+ Source
Ig
l l l l l l
hot e l
mhole
n+ Drain
Isub
– become highly energetic, i.e. hot
– cause impact ionization and generate e and holes
 holes go into the substrate creating substrate current, Isub.
• Some channel e have enough energy to overcome the
SiO2-Si energy barrier generating gate current, Ig.
• The maximum e-field, Em near the drain has the greatest
control of hot carrier effects.
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115
Hot Electron Effects: Substrate Current
• Local field model (DD)
Gn r   a [ r ] J n 
q
a ( )  a  e

c

c = critical electrical field  1.2 MV/cm
a = impact ionization coefficient.
– calibration of impact ionization model parameters are
required to match silicon data
– tuned parameter values can be non-physical and nonpredictive for a new technology.
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116
Hot Electron Effects: Isub using DD Model
DD simulation results with default Isub model parameters do not
match the measurement data.
Mumbai, India
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117
Hot Electron Effects: Substrate Current
• Local energy model (HD / ET model)
Gn r   a [un r ] J n 
q
a ( MOSFET )  a (bulk )
 “surface impact ionization”
– better predictive capability than DD approach, but still
uses tuned parameters.
• Non-local energy model.
• Full band MC.
Mumbai, India
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118
Hot Electron Effects: Summary
• Local field models are highly unphysical that result in
unphysical calibrated parameters.
• Local energy models are more physical, but still
require calibration of model parameters.
• Physically sound models that provide accurate
results without calibration of model parameters are:
– full band MC
– non-local energy transport models.
Mumbai, India
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119
Device TCAD: Summary
• As devices scale down to 0.1 mm and below, new
physical effects are coming into play.
• Existing tools treat different aspects of device
simulation fairly well.
• No single tool treats all of the important physics.
• Successful device TCAD will require a firm grasp of
the controlling device physics.
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120
Technology CAD: Technology Modeling,
Device Design and Simulation
Industry Application: Calibration of
Process and Device Models
2004 VLSI Design Tutorial, January 5, 2004
Mumbai, India
Samar Saha
Outline
• Objectives.
• Technology and Industry Trends affecting TCAD.
• TCAD Challenges.
• TCAD Tool Set.
• Calibration:
– Process Models
– Device Models.
• Mesh Generation.
• TCAD in Technology Development.
• Summary.
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Objectives
• Present issues and solutions for industrial TCAD:
– process simulation
 calibration
– device simulation
 key physical models
– mesh generation
 optimal approach
– calibration examples
 submicron process
 submicron device.
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Industry Trends affecting TCAD
• CMOS logic as technology driver:
– CMOS logic technology design-space much larger than
that of DRAM or BJT technologies
– CMOS logic generation life-span is extremely short
– CMOS simulation is essentially 2D.
• Logic technology offerings becoming broader:
– high-Vth devices
– thick-oxide devices
– low-Vth devices.
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124
Industry Trends affecting TCAD
• System-on-a-chip (SOC) and logic derivatives:
– integration issues driving increasing share of TCAD
cycles
 integrating memory and logic (NVRAM, DRAM)
 BiCMOS
 CMOS imaging
 SiGe BJT and PFET.
• Net result:
Rapidly expanding opportunities for TCAD to contribute.
Mumbai, India
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125
Industry Trends affecting TCAD
• Rapid thermal processing (RTP):
– easy process addition  increases design space
– many subtle electrical effects.
• Larger wafer sizes:
– interaction of process variations on circuit performance
becoming increasingly important  new TCAD arena.
• New impurity species  increase design options:
– In
– Ge
– N.
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126
Industry Trends affecting TCAD
• New materials and methods:
– nitrided gate oxide
– high-K gate dielectric
– junction pre-amorphization
– SOI
– selective epitaxial growth
– laser thermal annealing (LTA).
• Net result:
– rapidly expanding design space for TCAD to cover
– process TCAD challenges predominate.
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127
Industrial TCAD Challenges
• Challenge is to transform TCAD potential into
valuable results for process and device engineers.
• Key tasks:
– system perspective
 connect process recipes to device parametric/circuit
performance (“virtual fab”)
 organize TCAD process to make non-experts productive
TCAD users and maximize productivity of experts
– process and device simulations
 process simulation reflect actual process results
 accurate electrical results for compact model extraction.
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Industrial TCAD Challenges
• Critical assumptions for success:
– calibrate/characterize complex physical models for the
present range of operation - global calibration
– timely development/implementation of required physical
models
– timely calibration (local calibration) of process and device
models to contribute significantly for the next generation
 technology development
 technology transfer.
• TCAD usage can be significantly broadened.
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TCAD Tool Set
• Process simulation:
– 2D capability with
 extensive detailed physical model set for implantation,
diffusion, oxidation, deposition, and etching
 detailed knowledge
modification.
of
model
formulation
and
– examples based on
 vendor supported SUPREM4-process platform
 generalized calibration procedure.
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TCAD Tool Set
• Device Simulation:
– general 2D capability based on moments of Boltzmann
equation
– control-volume discretization of DD/HD equations
– examples based on
 vendor supported MEDICI-device platform
 generalized calibration procedure
– user environment
 vendor supported TWB-framework platform.
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Calibration - Role of TCAD
• TCAD in research:
– evaluate advanced device options
– understand device physics.
• TCAD in technology development (TD):
– perform tradeoffs for design options to
experimental wafer starts
– assess manufacturability and design options
– diagnose device/layout problems.
reduce
• TCAD in manufacturing:
– process simplification for production technologies
– problem diagnosis and fix.
 Accuracy is crucial, especially, for TD and manufacturing.
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Need for Calibration
• Deviation of simulation and measured data:
– technology dependent:
 different focus area and application
 different physical models involved.
– site/fab dependent:
 equipment
 material
 environment
 measurement techniques
 human interface.
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Need for Calibration
• Limitation of physical models:
– secondary mechanisms become important
– model dependency on implementation details
– model short-fall in describing the target generation of
process technology and devices.
• Limitation of model characterization/range:
– may not cover all possible process conditions
– may not cover all technologies
– may not be able to measure directly.
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134
Calibration Challenges
• Experimental data:
– expensive to obtain, especially, SIMS profiles
– insufficient processing information
– statistical fluctuations.
• Model complexity:
– some parameters can not be directly measured
– more parameters than data points.
• Simulation accuracy:
– grid dependency
– practical limitation on CPU and memory.
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Objective of Tool Calibration
• Device specific calibration:
– operation region (optimization)
– technology development
– items of importance.
• DOE and characterization.
• Calibration of model parameters.
• Supporting software utilities.
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General Calibration Methodology
• Use short flows to characterize process profiles:
– design process splits to cover design space.
• Use full flows to characterize devices with different
dimensions (L and W dependencies).
• Tool calibration:
– match SIMS profiles
– use device data to correlate 2D effects
– match device characteristics.
• Two-phase process.
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Process Simulation Overview
• Model calibration for process simulation:
– overview of calibration process
– Phase 1: 1D impurity calibration
 methodology
 example - nMOSFET channel profile
– Phase 2: 2D calibration (process + device)
 methodology
 example - reverse short channel effect (RSCE).
• Summary.
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138
Process Modeling Approach
• Predictive capability for a wide range of logic and
memory technologies necessitates:
– new implant tables with new species like In, Ge etc.
– 3-stream TED model for dopant, interstitials, and
vacancies
– “plus-n” damage model with accumulated damage from
multiple implants
– amorphization due to implant damage
– transient activation/deactivation of dopants
– dislocation loops as source/sink for interstitials
– 3-phase segregation model.
Mumbai, India
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139
Process Simulation Calibration: Overview
• Model calibration (Phase 1)
– implant models
– diffusion models
– oxidation models
– etch/deposition models.
 TEM/SEM cross-sections, SIMS profiles, key (1D)
electrical parameters.
• Technology/2D calibration (Phase 2)
– key process model parameters
– selected set of 2D electrical parameters.
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MOSFETs Process Model Calibration Flow
One-dimensional Calibration
Implant moments/table
OED
Segregation (set by channel profile)
Diffusivity (in oxide for dose loss)
Tox (QM,Poly-depletion corrections)
Two-dimensional Calibration
DIBL
Surface recombination
Damage by S/D implant
Match SIMS profiles
Adjust for dose loss
Match Vth
RSCE
One-dimensional Calibration
Diffusivity of dopant-defect pair
Diffusivity of defects
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141
MOSFETs 1D Process Model Calibration
n+
n+
p+
STI
p-well
p+
n-well
NMOS
PMOS
p-substrate
A B C
F E D
Cross-section for short loop experiments:
A / D  NMOS / PMOS channel
B / E  NMOS / PMOS SDE
C / F  NMOS / PMOS S/D.
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A Typical Short Loop Experiment for P-Well
Wafer No.
Sacrificial oxide
P-Well (B) implant
N-PT (B) implant
Well drive
nVth (BF2) implant
Gate oxidation
Poly re-oxidation
RTA1
Spacer dep/etch
S/D oxide
N+ (As) implant
RTA2
Mumbai, India
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Calibration Example: Channel Profile
• Use of detailed physical models to achieve 1D SIMS
profile fit:
– typical Phase-1 calibration activity
– model updated over several technology generations.
• Channel profile after complete technology thermal
cycle.
• Initial approach for implant and diffusion
– MC implant
 significant CPU burden
– scaled solid solubility
– physics-based implant moments / implant table update.
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144
Example: NMOS Channel Profile
log10 (Boron)
P-Well B, 1E13 @ 200 KeV
after spacer deposition/etch
SIMS
Simulation
Depth (mm)
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145
Technology Calibration - Phase 2
• Coupled process and device simulations using
Phase 1 calibration data.
• Target output (electrical) parameters:
– C - V curves
– Vth
– RSCE.
• Input variables (5 - 8 process model parameters):
– point-defect distributions from implants
 “plus-n” model
– key impurity segregation coefficients
– parabolic oxidation rate.
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146
2D Calibration Example: RSCE
Mumbai, India
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147
Process Modeling: Summary
• Systematic process model calibration methodology
is critical.
• Observed success within a (CMOS) technology:
– process re-optimization offered a significant improvement
in device performance
– process centering achieved at manufacturing co-location
with minimum development effort.
• Observation:
– each successive technology generation requires a
significant calibration effort (model update).
Mumbai, India
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148
Device TCAD
• Role of device simulation in TCAD
• Key physical models and examples:
– mobility models for deep sub-micron CMOS
– quantum effects in scaled CMOS devices
– DD model.
• Device model calibration:
– impact ionization with DD model.
• Summary.
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149
Device Simulation Role in TCAD
• Simulate device electrical behavior with sufficient
accuracy to calibrate process simulation models:
– primarily 2D electrostatic simulation
 Vth, DIBL, Ioff, body effect, capacitances
– expect DD model is sufficient for most requirements for
MOSFETs with Leff  0.1 mm.
• Provide capability for the physical simulation of wide
range of device parameters:
– substrate current, latch-up, ESD, and so on.
• Support exploratory device simulation for research.
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Device Simulation: CPU Burden
• Numerical issues associated with device simulation
are well established:
– core issue is repeated solution of large, sparse, illconditioned, non-symmetric sets of linear equations
– typical industrial CMOS problem:
 ~ 10,000 mesh nodes
 simultaneous solution for (, n, p)
– iterative solution methods often exhibit lack
convergence on problems of industrial interest.
of
• Optimized direct solution methods along with optimal
mesh generation techniques can reduce CPU
burden significantly without sacrificing accuracy.
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151
Critical TCAD Models: Carrier Mobility
• Device-design trends arising from CMOS scaling
require consideration of:
– coulombic scattering in the inversion layer
 high substrate/channel doping levels
 channel doping can vary significantly across the device
– inversion- and accumulation-layer mobility.
• Industrial use of a mobility model requires:
– strictly local calculation of mobility
 minor increase in program complexity
 no restrictions on device geometries or device designs.
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152
Critical Device TCAD Models: QM Effects
• CMOS scaling requires inclusion of inversion-layer
QM effects in device simulation for:
– thinner gate oxides
– higher substrate doping.
• Inversion-layer QM correction model must be:
– strictly local calculation of required physical quantities
 minor increase in program complexity
 no restrictions on device geometries or device designs
– acceptable CPU burden
– no significant degradation in robustness.
• Models: van Dort / MLDA.
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153
MOSFETs: Device Model Calibration Flow
IDS vs. VGS (Vth)
@ VBS = 0,VDS = 50 mV
IDS vs. VGS (IDS vs. VDS)
@ VBS = 0,VDS = VDD
IDS vs. VDS
@ VBS = 0,VGS = 0
Isub vs. VGS
@ VBS = 0,VGS = 0
Mumbai, India
Work function
QM model
Low field mobility
High field mobility
Band to band tunneling
Impact Ionization
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Example: Impact Ionization Model
DD-simulation over estimates Isub by more than an order.
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155
Example: Impact Ionization Model
• Impact Ionization model calibration:
– used calibrated process model (technology calibration)
– used calibrated device models (device calibration)
– calibrate impact ionization coefficients.
• The electron impact ionization rate:
 Bi
a i  Ai exp  
 Eeff
where




Ai and Bi are empirical constants
Eeff = effective electric field due to non-local effect.
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156
Example: Impact Ionization Model
For DD, transform the model in terms of local electric
field, E. Assume, Eeff a E,
Eeff = k * E

where
k and  are constants depending on the spatial variation
of E near the drain-end of the channel.
Substituting for Eeff and defining Bi  k
modified impact ionization coefficient is:
*
bi, the

 bi 
a i  Ai exp  

 E
Optimize bi and  to fit the measurement data.
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157
Example: Impact Ionization Model
Calibrate device TCAD models: comparison of I - V data.
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158
Example: Impact Ionization Model
Simulation with calibrated impact ionization coefficients.
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159
Example: Impact Ionization Model
Simulation with calibrated impact ionization coefficients.
Mumbai, India
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160
Device TCAD: Summary
• Vendor supported device TCAD tools work very well
with the present applications such as:
– MOSFET I - V and C - V characteristics for technology
development
 logic
 DRAM.
• Model selection and calibration show good results
for sub-0.25 mm technology development.
• Device TCAD effectiveness depends on:
– mobility model suitable for the target technology
– inversion-layer QM effects.
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161
Mesh Generation for Simulation
• Role and Requirements.
• Methods:
– structured
– quadtree
– unstructured
– hybrid.
• Example:
– typical MOSFET mesh and gridding considerations.
• Summary.
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Mesh Generation: Role and Requirements
• Requirement is to support complete automation of
process-to-device simulation transition:
– highest barriers to expanded TCAD usage are
 mesh generation
 process simulation accuracy.
• Consistent and specialized grid distribution is an
important key to simulation of high-performance
MOSET devices:
– resolution of inversion layers and depletion regions
– resolution of mobility-model physical effects.
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Mesh Generation: Role and Requirements
• Requirements:
– must accept device structures from detailed process
simulation
– no restrictions on device structures
– mesh generation approach must minimize computational
burden without compromising solution robustness and
accuracy
 key:
anisotropic grid-point distributions (the capability of
supporting extreme differences in grid-point spacing in
x- and y-directions).
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Mesh Generation Methods
Methods
Structured:
- algebraic
- elliptic
Unstructured
-
Advantages
Precise grid control
Smooth grid transition
Supports anisotropic grid
scales.
Very general
Easy to automate.
-
Quadtree/Octree:
- isotropic
recursive
subdivision
Hybrid:
- recursive
subdivision for
anisotropy
- unstructured
mesh algorithm
Mumbai, India
- Very general
- Easy to automate.
-
-
Very general
Easy to automate
Precise and smooth grids
Supports grid scales
Minimizes mesh sizes
Minimizes CPU burden.
Samar Saha
Disadvantages
Requires significant
structural preprocessing
Difficult to automate
Large grid sizes.
Do not support anisotropic
grids
Large grid size for industrial
problems.
Needs advanced features to
support anisotropic grids
Large grid size for industrial
problems.
Need to identify different
regions for gridding prior to
device simulation.
165
Gate
Mumbai, India
Channel
Hybrid Mesh Generation: Half-MOSFET
x
S/D
Source/Drain
y
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166
Mesh Generation
Dependence of device performance on vertical grid-spacing.
Mumbai, India
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167
Mesh Generation
Dependence of device performance on horizontal grid-spacing.
Mumbai, India
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Mesh Generation: Summary
• Mesh generation is the critical component of an
effective TCAD system.
• Simulation results vary significantly on mesh and
may result in:
– unphysical calibration parameters
– unpredictable/inconsistent results.
• Robust mesh:
– allows process simulators to be consistently and robustly
linked to device simulators by non-experts
– significantly reduces CPU burden for device simulation.
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169
Industry Application: Summary
• Vendor supported TCAD tools offer most simulation
capabilities for industrial usage.
• Systematic calibration procedure is required to
support efficient:
– process technology optimization
– future technology development.
• Mesh generation is crucial for predictive technology
simulation.
• Well calibrated physical models provide efficient
predictive TCAD capability.
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170
Technology CAD: Technology Modeling,
Device Design and Simulation
Industry Application: TCAD in Device
Research and Compact Modeling
2004 VLSI Design Tutorial, January 5, 2004
Mumbai, India
Samar Saha
Research Application: Overview
• Role of TCAD in device research:
– how it differs from development/manufacturing.
– examples
 sub-100 nm MOSFET device design
 design optimization of FinFETs.
• TCAD for compact modeling:
– TCAD-based compact model parameter extraction for
substrate current modeling
– flash memory cell macro model.
• Summary.
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Role of TCAD in Research
• Performance analysis of future device design
options to guide development effort.
• Understand device physics for new device concepts.
• Typically, research TCAD is not the “virtual fab”
paradigm:
– process simulation is not used, since device cannot be
made with current process technologies.
• Circuit performance is directly evaluated from the
output of device simulation using two different ways:
1 device simulation  model extraction  circuit simulation
2 mixed-mode device/circuit simulation.
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Example: Sub-100 nm MOSFET Design
• Design issues in achieving MOSFET devices near
the lower limit of channel length:
– scaling requirements
– material limitations of scaling
– feasibility of continuous scaling.
• Methodology to generate sub-100 nm MOSFET
device characteristics vs. scaling parameters.
• Results and discussions.
• Summary.
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Scaling Requirements vs. Limitations
Scaling Requirements
Present Limitations
A reduction in gate oxide SiO2-Tox(eff) 2 nm to maintain:
thickness, TOX in proportion to  tolerable chip standby power ~
100 mW range
the gate length, Lg to:
 control threshold voltage, Vth
 control drain-induced barrier
lowering (DIBL)
 improve drive current, IDSAT.
 tolerable direct-tunneling gate
leakage current, Ig ~ 1 A/cm2
 off-state leakage current, Ioff ~ 1
nA/mm.
A reduction in source-drain Xj  30 nm to maintain:
extension junction depth, Xj  lower source-drain series
resistance, RSD
with scaling Lg to control:
 short channel effect (SCE).
 higher IDSAT.
A reduction in Lg to:
Lg  60 nm to maintain:
 improve device performance.
Mumbai, India
 Xj  30 nm
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Feasibility of Continuous TOX and Xj Scaling
• Scaling Tox(eff)  2 nm is feasible with a highK
dielectric gate material to maintain:
– a thicker value of TOX(physical) for a tolerable value of Lg
– a target value of gate capacitance (COX) equivalent to
that of an ultra-thin SiO2 gate material.
• Scaling Xj  30 nm is essential to:
– scale down Lg, gate area, and COX
– improve ac device performance.
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Idealized Device Simulation Structure
Lg
Lext
Poly-Si gate Spacer
Xj
Xjd
TOX
SDE
Halo
Halo
DSD
Leff
Body (B)
• Channel doping profile: vertically and laterally non-uniform.
• SDE: heavily-doped source-drain extension regions with
junction depth Xj.
• DSD: heavily-doped deep source-drain of junction depth Xjd.
• Halo: channel-type doping around SDE regions.
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Design Simulation Experiment
• Designed CMOS technologies for Leff = 25 nm with:
– {Lg = 40 nm, Xj @ 14 nm, Tox(eff) = {1,1.5, 2} nm}
– {Lg = 50 nm, Xj @ 20 nm, Tox(eff) = {1,1.5, 2} nm}
– {Lg = 60 nm, Xj @ 26 nm, Tox(eff) = {1,1.5, 2} nm}.
• For each technology:
– non-uniform vertical channel doping profile
optimized for the target long channel |Vth| @ 0.23 V
was
– two halo profiles (double halo architecture) were used to
 reduce DIBL from both SDE and DSD regions
 achieve non-uniform lateral channel doping profile with
the target |Ioff| @ 10 nA/mm @ |VDD| = 1 V.
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Simulation Strategy
• Optimized technology parameters:
– SDE peak concentration @ 2.5x1020 cm-3
– DSD peak concentration @ 3.7x1020 cm-3
– peak halo concentration @ 5x1018 - 1x1019 cm-3.
• Channel concentration  dependent on Lg.
• Device characteristics were generated using MEDICI
with:
– hydrodynamic model for semiconductors
– van Dort’s Quantum Mechanical model
– calibrated device models (global calibration!!).
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Simulated Channel Doping Contours
Lg
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Simulated Vth vs. Leff for different TOX(eff)
0.45
0.45
nMOSFET
0.35
0.25
0.25
T ox(eff) = 2.0 nm
T ox(eff) = 1.5 nm
T ox(eff) = 1.0 nm
0.05
(a)
-0.05
40 nm T echnology; Xj @14 nm
-0.15
0.05
(b)
-0.05
60 nm T echnology; Xj @26 nm
-0.15
|VDS| = 0.05 V; VBS = 0
-0.25
T ox(eff) = 2.0 nm
T ox(eff) = 1.5 nm
T ox(eff) = 1.0 nm
0.15
Vth (V)
0.15
Vth (V)
nMOSFET
0.35
|VDS| = 0.05 V; VBS = 0
-0.25
-0.35
-0.35
pMOSFET
-0.45
10
20
30
40
50
60
70
pMOSFET
-0.45
80
90
100
Leff (nm)
10
20
30
40
50
60
70
80
90
100
Leff (nm)
• |Vth| increases with the increase in TOX(eff) for all devices.
• Devices with Leff = 25 nm and TOX(eff) = 2 nm, |Vth| > 0.4 V is
too high for high-performance operation @ |VDD|  1 V.
• TOX(eff) < 2 nm offers lower |Vth| for low power operation.
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Simulated IDSAT vs. Ioff for different TOX(eff)
•
Devices with |Ioff| @ 10 nA/mm represents Leff = 25 nm.
•
At a constant |Ioff|  2 nA/mm:
– |IDSAT| increases as TOX(eff) decreases
– TOX(eff) < 2 nm is essential to improve IDSAT for Leff = 25 nm
devices.
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Simulated I - V Data for TOX(eff) = 1 nm
• For a typical 50 nm technology with Leff = 25 nm and Tox(eff) = 1
nm:
– S @ 80 mV/decade
– |DIBL| @ 60 mV
– IDSAT(n) @ 680 mA/mm, |IDSAT(p)| @ 275 mA/mm @ |VGS| = 1 V = |VDS|.
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Simulated I - V Data for TOX(eff) = 1.5 nm
• For 25 nm devices of a 50 nm CMOS technology, as Tox(eff)
increases from 1 nm  1.5 nm:
– S increases [DS @ 8 mV/decade]
– DIBL increases [D(DIBL) @ 30 mV]
– |IDSAT| decreases [DIDSAT(n) @ 102 mA/mm; DIDSAT(p) @ 42 mA/mm].
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Simulated I - V Data for TOX(eff) = 2 nm
• For 25 nm devices of a 50 nm CMOS technology, as Tox(eff)
increases from 1 nm  2 nm:
– S increases [DS @ 16 mV/decade]
– DIBL increases [D(DIBL) @ 60 mV]
– |IDSAT| decreases [DIDSAT(n) @ 214 mA/mm; DIDSAT(p) @ 72 mA/mm].
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Simulated Vth vs. Xj for Different TOX(eff)
nMOSFET
0.45
0.35
0.25
Vth (V)
0.05
-0.05
|VDS| = 0.05 V; V BS = 0
-0.15
L eff = 25 nm; |I off | @ 10 nA/mm
-0.25
pMOSFET
Tox(eff) = 2.0 nm
Tox(eff) = 1.5 nm
Tox(eff) = 1.0 nm
0.15
-0.35
-0.45
12
14
16
18
20
22
24
26
28
X j (nm)
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Simulated IDSAT vs. Xj for Different TOX(eff)
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Simulated DIBL vs. Xj for Different TOX(eff)
150
dVth (DIBL) (mV/V)
130
110
90
70
Tox(eff) = 2.0 nm
Tox(eff) = 1.5 nm
Tox(eff) = 1.0 nm
Tox(eff) = 2.0 nm
Tox(eff) = 1.5 nm
Tox(eff) = 1.0 nm
50
30
10
12
14
16
(nMOSFET)
(nMOSFET)
(nMOSFET)
(pMOSFET)
(pMOSFET)
(pMOSFET)
18
20
L eff = 25 nm
VBS = 0
22
24
26
28
X j (nm)
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Simulated S vs. Xj for Different TOX(eff)
100
S (mV/decade)
95
90
85
80
Tox(eff) =
Tox(eff) =
Tox(eff) =
Tox(eff) =
Tox(eff) =
Tox(eff) =
75
70
65
2.0 nm
1.5 nm
1.0 nm
2.0 nm
1.5 nm
1.0 nm
(nMOSFET)
(nMOSFET)
(nMOSFET)
(pMOSFET)
(pMOSFET)
(pMOSFET)
Leff = 25 nm
VBS = 0
60
12
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18
20
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X j (nm)
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Simulated Delay for Different Xj and Lg
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Sub-100 nm MOSFET Design: Summary
• The simulation results show the feasibility of 25 nm
MOSFETs with:
– TOX(eff)  2 nm to
 maintain lower |Vth| for |VDD|  1 V operation
 achieve higher |IDSAT| for a target value of |Ioff|
 lower value of DIBL
 lower value of S @ 80 mV/decade
– Xj  30 nm to
 scale Lg  60 nm
 improve device speed.
• 25 nm devices with Xj @ 14 nm and Lg @ 40 nm show
a significant improvement in speed.
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Example: Double Gate MOSFET Design
• Design FinFET (double-gate MOSFET) Simulation
Structure.
• Optimize Different Fin-dimensions.
• Feasibility of 20 nm FinFET Device.
• Comparison of 20 nm Device Performance using
FinFET vs. Conventional MOSFET Architecture.
• Summary.
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Idealized Double Gate MOSFET Structure
Top Gate
Tox
TSi
Source
Drain
Tox
Bottom Gate
Lg
• Tox = Top/bottom gate oxide thickness.
• TSi = Un-doped/lightly-doped channel width.
• Lg = Channel length.
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Simulated DG-MOSFET FinFET Structure
Tfin
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Major Process Steps to Generate FinFETs
3. Poly-Si gate
2. Gate oxidation
BOX
Nitride
5. Half-structure
4. Nitride spacer
S/D implant
1. Define Si-Fin
Poly
6. Full-structure
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Critical Parameters for FinFET Simulation
• Parameters used for simulation structure design:
– Tfin = 10 to 30 nm
– Hfin = 50 nm
– Lg = 10 to 50 nm
– Tox = 1.5 nm.
• For device simulation, channel doping was optimized
to obtain Vth @ 0.1 V for Lg = 20 nm nFinFETs.
• Device structures and the characteristics were
generated using 3D-simulation tool Taurus (from
Synopsys).
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Vth (V)
Vth vs. Lg for Different Tfin; Hfin = 50 nm
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
Tfin = 10 nm
Tfin = 20 nm
Tfin = 30 nm
10
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L (Gate) (nm)
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50
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IDSAT vs. Lg for Different Tfin; Hfin = 50 nm
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S vs. Lg for Different Tfin; Hfin = 50 nm
S (mV/decade)
150
Tfin = 10 nm
130
Tfin = 20 nm
Tfin = 30 nm
110
90
70
50
10
20
30
40
50
L (Gate) (nm)
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I  V Characteristics of 20 nm FinFETs
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FinFETs vs. Conventional MOSFETs
Device
Parameters
Units
Leff
Tox
Vth
IDSAT (VGS = VDS = 1 V)
Ioff (VGS = 0, VDS = 1 V)
DIBL
S-factor
nm
nm
V
mA/mm
mA/mm
V
mV/decade
FinFETs
20
1.5
0.13
775
3
32
83
Double-halo
MOSFETs
20
1.5
0.35
587
0.05
130
100
20 nm FinFETs show superior device performance
compared to 20 nm conventional MOSFETs.
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FinFET Design: Summary
• TCAD is used to design and study FinFET device
characteristics.
• The simulation data for nFinFETs with 10 nm < Lg <
50 nm and Hfin = 50 nm show:
– higher Vth roll-off as Lg decreases for thicker Tfin devices
– lower IDSAT in thinner Tfin devices due to higher s/d
resistance
– increase in S with decrease in Lg for Tfin < 50-nm
– S  60 mV/decade for all Tfin with Lg >>40-nm.
• 20 nm FinFETs show superior device performance
than 20 nm conventional bulk-MOSFETs.
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Example: Compact Model Extraction for Isub
• Procedure for TCAD-based
Parameter Extraction.
Compact
Model
• Simplification of Isub Model for TCAD-based Compact
Modeling.
• Model Extraction.
• Model Verification.
• Summary.
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Substrate Current, Isub Model
Isub generated due to impact ionization is given by:
 Bi 
Ai
I sub  lc Em I DS exp 
,
Bi
 Em 
where
Ai and Bi are impact ionization parameters
lc = characteristic length of saturation region
Em = maximum lateral electric field near the drain
2
 VDS  VDSAT 
  Ec2
 
lc


Ec = critical electric field for velocity saturation.
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Substrate Current, Isub Model
At strong inversion (VDS >> VDSAT) Em is given by:
VDS  VDSAT
Em @
lc


Ai
Bi lc
 I sub  VDS  VDSAT I DS exp 

Bi
 VDS  VDSAT 
where
VDSAT 
Ec Leff VGS  Vth 
Ec Leff  VGS  Vth 
Leff = effective channel length of device
Vth = threshold voltage of device.
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Substrate Current, Isub Model
• The bias dependence of Ec is given by:
Ec = Ec0 + EcgVGS + EcbVBS
where Ec0, Ecg, and Ecb are model parameters given
by:
Ec0 = Ec @ VGS = VBS = 0
Ecg = slope of Ec vs. VGS plot @ VBS = constant
Ecb = slope of Ec vs. VBS plot @ VGS = constant
• The bias dependence of lc is given by:
lc = (lc0 + lc1VDS)TOX
here lc0 and lc1 are model parameters.
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Isub Model Parameters
• Empirical constants:
– Ai = 1.65x106 (1/cm)
– Bi = 1.66x106 (V/cm)
• Technology dependent parameters:
– Ec0 = bias independent constant (V/cm)
– Ecg= gate bias dependent parameter (1/cm)
– Ecb = back-gate bias dependent parameter (1/cm)
– lc0 = bias independent constant (cm)
– lc1 = bias dependent constant (cm/V).
We assume, lc = lc0 is a technology dependent constant
for TCAD-based parameter extraction (i.e. ignore lc1).
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TCAD-based Isub Model Extraction
Process Model
Calibration
Process
Simulation
Generate:
Device Structure
Device Model
Calibration
Device
Simulation
At each VGS, generate:
IDS - VDS and Isub - VDS
Format I - V data
Compute Isub/IDS
Extraction of
{Ec0, Ecg, Ecb}
VDSAT extraction
Ec extraction
lc extraction
SPICE simulation
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Parameter Extraction: VDSAT
VDSAT is extracted by mapping constant Isub/IDS contours on
IDS vs. VDS family of simulated curves.
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Parameter Extraction: Ec0, Ecg, and Ecb
• Ec0 and Ecg extraction:
– extract VDSAT for different values of VGS at VBS = 0.
– compute Ec from:
VDSAT 
Ec Leff VGS  Vth 
Ec Leff  VGS  Vth 
– plot Ec vs. VGS to extract:
Ec0 = intercept @ VGS = 0
Ecg = slope.
• Same procedure to extract Ecb with VBS  0.
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Parameter Extraction: lc and Components


Ai
Bi lc
I sub  VDS  VDSAT I DS exp 

Bi
V

V
DSAT 
 DS
• The simplified from of the expression:
log(Y) = mX + C,
where
X = 1/(VDS - VDSAT)
Y = Isub/[IDS(VDS - VDSAT)]
• Parameters are extracted from log(Y) vs. X plots:
slope, m = - Bi lc
intercept, C = ln(Ai/Bi).
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Parameter Extraction: lc and Components
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TCAD-based Isub Models
• For nMOSFET devices of the target technology:
+ Ec0 = 5.50E+04 (V/cm)
+ Ecg = 3.50E+03 (1/cm)
+ lc = 1.38E-05 (cm)
+ Ai = 1.65E+06 (1/cm)
+ Bi = 1.66E+06 (V/cm)
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Model Verification
Measurement and simulation data using the extracted models.
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Model Verification
Measurement and simulation data using the extracted models.
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Model Extraction for Isub: Summary
• The example shows the basic idea to use TCAD for
compact model parameter extraction using:
– calibrated process models for process TCAD
– calibrated device models for device TCAD
– simplified equations and extraction routines, as needed.
• Process and device models were calibrated for the
target technology.
• Isub model is simplified to extract model parameters.
• The simulation data using TCAD-based model agree
very well with the measurement data.
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Example: Flash Memory Cell - Macro Model
• Flash Memory Cell Compact Modeling
– split gate cell
– two-transistor macro model
– necessity for TCAD-based macro model.
• Model extraction.
– procedure.
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Flash Memory Cell - Split Gate Structure
• Cell consists of:
– WL transistor
– FG transistor.
• FG may not have
contact pad for
measurement.
• Typically, 1T-cell
model is used.
• 2T-model provides
more accurate cell
characteristics.
 TCAD-based.
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Calibrated
Process Model
Calibrated
Device Model
SPICE/Circuit
Simulation
Simulate
Test Structures
Simulate
I - V for T1
Simulate
I - V for T2
Extract SPICE
Model for T1
Extract SPICE
Model for T2
Calibrated
Device Model
Flash Memory Cell: TCAD-based Model
Generate
Macro Model
Model Verification
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TCAD in Research & Modeling: Summary
• Device TCAD can be successfully used in device
research to:
– study different device options
– examine new device ideas
– optimize device design range for technology
development guideline.
• Calibrated TCAD models can be used accurately to:
– predict device performance
– extract compact model
– predict circuit performance.
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