Transcript Junction Capacitances

Junction Capacitances
• The n+ regions forms a number of
planar pn-junctions with the
surrounding p-type substrate
numbered 1-5 on the diagram.
• Planar junctions 2, 3 and 4 are
surrounded by the p+ channel stop
implant.
• Planar junction 1 is facing the
channel while the bottom planar
junction 5 is facing the p-type
substrate with doping NA.
• The junction types will be n+/p,
n+/p+, n+/p+ n+/p+ and n+/p.
Junction Capacitances
• The voltage dependent sourcesubstrate and drain-substrate
junction capacitances are due to
depletion charge surrounding the
source or drain diffusion regions
embedded in the substrate.
• The source-substrate and drainsubstrate junctions are reverse
biased under normal operating
conditions.
• The amount of junction
capacitance is a function of
applied terminal voltages
• All junctions are assumed to be
abrupt.
• Given that the depletion thickness
is xd we can compute the
depletion capacitance of a reverse
biased abrupt pn-junction.
xd 
2 Si N A  N D
0  V 
q NAND
• Where NA and ND are the n-type
and p-type doping densities
respectively, V is the negative
reverse bias voltage.
• The built-in junction potential is:
0 
kT  N A N D
ln 
q  ni2



Junction Capacitances
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The junction is forward biased for a
positive voltage V and reverse biased
for a negative voltage V.
The depletion region charge stored in
this area in terms of xd is
 N N 
 N N 
Q j  Aq A D  xd  A 2 Si q A D 0  V 
D 
A  ND 
 N A  Nfor
 Narea.
• A stands
the junction
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The junction capacitance associated
with the depletion region is defined
dQ
as: C j  j
dV
If we differentiate the equation
describing Qj with respect to the bias
voltage we get Cj.
•
If the zero bias capacitance is:
C j0 
•
 Si q  N A N D  1 

 
2  N A  N D  0 
We can write the junction capacitance
C j V   A
 Si q  N A N D  




2  N A  N D   0  V 
1
in a more general form as
C j (V ) 
AC j 0
 V 
1  
 0 
m
m is the gradient coefficient and is 0.5
for abrupt junctions and 1/3 for
linearly graded junction profiles
• The value of the junction capacitance
ultimately depends on the external
bias voltage applied across the pnjunction.
Junction Capacitances
• The sidewalls of a typical
MOSFET source or drain
diffusion region are surrounded
by a p+ channel stop implant
having a higher doping density
than the substrate doping density
NA.
• The sidewall zero bias
capacitance is Cj0sw and will be
different from the previously
discussed junction capacitance.
• The zero-bias capacitance per unit
area can be found as follows:
C j 0 sw 
 Si q  N A( sw) N D  1
2  N A( sw)  N D  0( sw)
• Where NA(sw) is the sidewall
doping density, 0(sw) is the builtin potential of the sidewall
junctions.
• All sidewalls in a typical diffusion
structure have approximately the
same junction depth xj.
• The zero bias sidewall junction
capacitance per unit length is:
C jsw  C j 0 sw x j
Non-Ideal I-V Effects (Summary)
• Miniaturization has led to modern
devices having nonideal
characteristics
• The saturation current increases
less than quadratically with
increasing VGS.
• Velocity saturation and mobility
degradation are two of the effects
that cause the non quadratic
current increase with VGS.
• When carrier velocity ceases to
increase linearly with field
strength we have velocity
saturation.
• The current IDS is lower than
expected at high VDS.
• There are several sources of
leakage that result in current flow
when the transistor is expected to
be OFF.
• The source and drain diffusion
regions are form reverse biased
diodes which experience junction
leakage into the substrate or well.
• The current into the gate IG is
ideal zero, however as gate oxide
thickness is reduced electrons
tunnel through the gate, causing
some current.
Velocity Saturation
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The critical E-field at which
scattering effects occur depends on
the doping levels and the vertical
electric field applied.
Velocity saturation effects are less
pronounced in pMOS devices.
By increasing VDS the electrical field
in the channel ultimately reaches the
critical value and the carriers at the
drain become velocity saturated.
Further increasing VDS does not result
in increased ID. The current saturates
at IDSAT
The behavior of the MOS transistor is
better understood by analysis of the IV curves.
Sub-Threshold Conduction
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Ideally at VGS < VT, ID = 0.
The MOS device is partially
conducting for gate voltages below
the threshold voltage.
This is termed sub-threshold or weak
inversion conduction.
In most digital applications the
presence of sub-threshold current is
undesirable. Why?
….most digital applications …. Does
this mean some digital applications
can tolerate sub-threshold currents?
A Sub-threshold digital circuit
manages to satisfy the ultra-low
power requirement. How?
•
What type of digital applications can
benefit from this ultra low power
design approach?