Transcript 5 6 7 Integration 8 Reconfiguration 9 Prototype Tasks

CLBv2 block diagram+tasks
IP/UDP Packet Buffer
Stream Selector (IPMUX)
Distribute
UTC?
RxPort 1
Fifo
RxPort 2
Management
& Control
RxPort_m
Tx Stream Select
Tx_data2buf
Tx_pkt2mac
ADC
Management
& Control
TxPort 1
TxPort 2
TxPort_m
Fifo
Management
& Config.
6
Management
& Control
October 3, 2012 P. Jansweijer
CPU
UART
RS232
Debug
Data
Control
AMBA/Wishbone bus
UTC time & Clock
MEM
1A
5
Compas,
Tilt, Temp
2
Flags
Data
Hydrophone
Fifo
1
31
TDC
Management
& Config.
Pause Frame?
TxPacket
Buffer
32KB
4
31 TDCs
31 PMTs
Rx Stream Select
Flags
Rx_buf2data
Rx_mac2buf
RxPacket
Buffer
64KB
3
I2C
7 Integration
8 Reconfiguration
9 Prototype
Tasks:
1 LM32
1A LM32 Slow Control
2 White Rabbit
3 IPMUX Externe IO
4 TDC's
5 ADC's
6 Other instrumentation
7 System integration
8 Reconfigure
9 Prototype:
Design
Order components
PCB
Assembly
10 Test prototype
Test software
Stand alone test
System integration with Shore station
System test
IP/UDP routing proposal
PC2
IP=
192.16.x.1
IP=
192.16.x.2
PCn
IP=
192.16.x.n
PC1
Switch
GPS
Buffers!
How big?
10MHz
PPS
WR Switch
DOM
1
DOM
2
WR Switch
DOM
16
DOM
11985
DOM
11986
DOM
12000
1.
Each DOM synchronizes to the absolute time (using White Rabbit)
Time Slice
IP Address
IP
2.
Each DOM receives a look up table with IP addresses while configuring the
detector.
Time1Slice
192.16.x.1
IP
2
192.16.x.2
All DOMs start at an absolute point in time which was communicated via a
command over the White Rabbit network.
:
:
n
192.16.x.n
3.
4.
All DOMs start their first time-slice at exactly the same time.
5.
All data is IP/UDP formatted and passed to the IP number corresponding to the
time slice
6.
After ‘n’ time slices, PC1 is again selected to process the data
October 3, 2012
IP/UDP routing proposal
PC1
PC2
PCn
192.16.x.1
192.16.x.2
192.16.y.z
Servers may be
used for storage and
Pre-processing
Switch
Server
GPS
10MHz
PPS
Server
Buffers!
Where and
How big?
Server
WR Switch
DOM
1
DOM
2
Server
WR Switch
DOM
16
DOM
11985
DOM
11986
DOM
12000
1.
Each DOM synchronizes to the absolute time (using White Rabbit)
Time Slice
IP Address
IP
2.
Each DOM receives a look up table with IP addresses while configuring the
detector.
Time1Slice
192.16.x.1
IP
2
192.16.x.2
All DOMs start at an absolute point in time which was communicated via a
command over the White Rabbit network.
:
:
n
192.16.y.z
3.
4.
All DOMs start their first time-slice at exactly the same time.
5.
All data is IP/UDP formatted and passed to the IP number corresponding to the
time slice
6.
After ‘n’ time slices, PC1 is again selected to process the data
October 3, 2012
LM32, three boot types
1.
2.
3.
October 3, 2012
Generate ROM image before synthesis (used for functional simulation debug)
 Describe a generic RAM using “init” file
 Useful for functional simulation
 Incorporates “boot.elf” in the block-rams
After Place&Route (will be used in final CLB)
 Merge “FPGA.bit” file and “boot.elf” file (data2mem)
 This needs BMM=Block Memory Mapping file
 The “bit” file which is outputted by the merge can be used as updated
configuration file
 This avoids synthesis each time software is updated
Download “elf” via an external interface in a running system (used for software
debug)
 This only applies to a system that has such external interface (the CLBv2 in
situ doesn’t)
 Useful for debugging purposes (the SPEC uses PCIe or via JTAG)
 No BMM=Block Memory Mapping file needed