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CS252 Graduate Computer Architecture Lecture 24 Network Interface Design Memory Consistency Models Prof John D. Kubiatowicz http://www.cs.berkeley.edu/~kubitron/cs252 Message passing • Sending of messages under control of programmer – User-level/system level? – Bulk transfers? • How efficient is it to send and receive messages? – Speed of memory bus? First-level cache? • Communication Model: – Synchronous » Send completes after matching recv and source data sent » Receive completes after data transfer complete from matching send – Asynchronous » Send completes after send buffer may be reused 4/27/2009 cs252-S09, Lecture 24 2 Synchronous Message Passing Source Destination Recv Psrc, local VA, len (1) Initiate send (2) Address translation on P src Send Pdest, local VA, len (3) Local/remote check Send-rdy req (4) Send-ready request (5) Remote check for posted receive (assume success) Wait Tag check Processor Action? (6) Reply transaction Recv-rdy reply (7) Bulk data transfer Source VADest VA or ID Data-xfer req • • • • 4/27/2009 Time Constrained programming model. Deterministic! What happens when threads added? Destination contention very limited. User/System boundary? cs252-S09, Lecture 24 3 Asynch. Message Passing: Optimistic Destination Source (1) Initiate send (2) Address translation Send (Pdest, local VA, len) (3) Local /remote check (4) Send data (5) Remote check for posted receive; on fail, allocate data buffer Tag match Data-xfer req Time Allocate buffer Recv P src, local VA, len • More powerful programming model • Wildcard receive => non-deterministic • Storage required within msg layer? 4/27/2009 cs252-S09, Lecture 24 4 Asynch. Msg Passing: Conservative Destination Source (1) Initiate send (2) Address translation on P dest Send Pdest, local VA, len (3) Local /remote check Send-rdy req (4) Send-ready request (5) Remote check for posted receive (assume fail); record send-ready Return and compute Tag check (6) Receive-ready request Recv Psrc, local VA, len (7) Bulk data reply Source VADest VA or ID Recv-rdy req Data-xfer reply • Where is the buffering? • Contention control? Receiver initiated protocol? • Short message optimizations Time 4/27/2009 cs252-S09, Lecture 24 5 Features of Msg Passing Abstraction • Source knows send data address, dest. knows receive data address – after handshake they both know both • Arbitrary storage “outside the local address spaces” – may post many sends before any receives – non-blocking asynchronous sends reduces the requirement to an arbitrary number of descriptors » fine print says these are limited too • Optimistically, can be 1-phase transaction – Compare to 2-phase for shared address space – Need some sort of flow control » Credit scheme? • More conservative: 3-phase transaction – includes a request / response • Essential point: combined synchronization and communication in a single package! 4/27/2009 cs252-S09, Lecture 24 6 Active Messages Request handler Reply handler • User-level analog of network transaction – transfer data packet and invoke handler to extract it from the network and integrate with on-going computation • Request/Reply • Event notification: interrupts, polling, events? • May also perform memory-to-memory transfer 4/27/2009 cs252-S09, Lecture 24 7 Common Challenges • Input buffer overflow – N-1 queue over-commitment => must slow sources • Options: – reserve space per source (credit) » when available for reuse? • Ack or Higher level – Refuse input when full » backpressure in reliable network » tree saturation » deadlock free » what happens to traffic not bound for congested dest? – Reserve ack back channel – drop packets – Utilize higher-level semantics of programming model 4/27/2009 cs252-S09, Lecture 24 8 Spectrum of Designs • None: Physical bit stream – blind, physical DMA nCUBE, iPSC, . . . • User/System – User-level port – User-level handler CM-5, *T, Alewife, RAW J-Machine, Monsoon, . . . • Remote virtual address – Processing, translation Paragon, Meiko CS-2 • Global physical address – Proc + Memory controller RP3, BBN, T3D • Cache-to-cache – Cache controller Dash, Alewife, KSR, Flash Increasing HW Support, Specialization, Intrusiveness, Performance (???) 4/27/2009 cs252-S09, Lecture 24 9 Net Transactions: Physical DMA Data Dest DMA channels Addr Length Rdy Memory Status, interrupt Cmd P Addr Length Rdy Memory P • DMA controlled by regs, generates interrupts • Physical => OS initiates transfers sender auth • Send-side dest addr – construct system “envelope” around user data in kernel area • Receive – receive into system buffer, since no interpretation in user space 4/27/2009 cs252-S09, Lecture 24 10 nCUBE Network Interface Input ports Output ports Switch Addr Addr Addr DMA channels Addr Length Addr Length Addr Length Memory bus Memory Processor • independent DMA channel per link direction – leave input buffers always open – segmented messages • routing interprets envelope Os 16 ins 260 cy 13 us Or 200 cy 15 us 18 - includes interrupt – dimension-order routing on hypercube – bit-serial with 36 bit cut-through 4/27/2009 cs252-S09, Lecture 24 11 Conventional LAN NI Host Memory NIC trncv NIC Controller Data addr TX RX Addr Len Status Next Addr Len Status Next Addr Len Status Next Addr Len Status Next Addr Len Status Next DMA len IO Bus mem bus Proc Addr Len Status Next • Costs: Marshalling, OS calls, interrupts 4/27/2009 cs252-S09, Lecture 24 12 User Level Ports Virtual address space User/system Data Dest Net output port Net input port Mem P Status, interrupt Processor Status Mem P Registers Program counter • initiate transaction at user level • deliver to user without OS intervention • network port in user space – May use virtual memory to map physical I/O to user mode • User/system flag in envelope – protection check, translation, routing, media access in src CA – user/sys check in dest CA, interrupt on system 4/27/2009 cs252-S09, Lecture 24 13 Example: CM-5 • Input and output FIFO for each network • 2 data networks • tag per message Diagnostics network Control network Data network PM PM Processing partition Processing Control partition processors I/O partition – index NI mapping table • context switching? SPARC FPU $ ctrl • Alewife integrated NI on chip • *T and iWARP also Data networks $ SRAM NI MBUS DRAM ctrl Vector unit DRAM DRAM ctrl DRAM Vector unit DRAM ctrl DRAM Os 50 cy 1.5 us Or 1.6 us 53 cy interrupt 4/27/2009 Control network cs252-S09, Lecture 24 DRAM ctrl DRAM 10us 14 RAW processor: Systolic Computation • Very fast support for systolic processing – Streaming from one processor to another » Simple moves into network ports and out of network ports – Static router programmed at same time as processors • Also included dynamic network for unpredictable computations (and things like cache misses) 4/27/2009 cs252-S09, Lecture 24 15 User Level Handlers U s e r /s y s te m D a ta A d d re s s D e st M em Mem P P • Hardware support to vector to address specified in message – On arrival, hardware fetches handler address and starts execution • Active Messages: two options – Computation » Handler – Computation » Handler 4/27/2009 in background threaads never blocks: it integrates message into computation in handlers (Message Driven Processing) does work, may need to send messages or block cs252-S09, Lecture 24 16 J-Machine • Each node a small mdg driven processor • HW support to queue msgs and dispatch to msg handler task 4/27/2009 cs252-S09, Lecture 24 17 Alewife Messaging • Send message – write words to special network interface registers – Execute atomic launch instruction • Receive – Generate interrupt/launch user-level thread context – Examine message by reading from special network interface registers – Execute dispose message – Exit atomic section 4/27/2009 cs252-S09, Lecture 24 18 Sharing of Network Interface • What if user in middle of constructing message and must context switch??? – Need Atomic Send operation! » Message either completely in network or not at all » Can save/restore user’s work if necessary (think about single set of network interface registers – J-Machine mistake: after start sending message must let sender finish » Flits start entering network with first SEND instruction » Only a SENDE instruction constructs tail of message • Receive Atomicity – If want to allow user-level interrupts or polling, must give user control over network reception » Closer user is to network, easier it is for him/her to screw it up: Refuse to empty network, etc » However, must allow atomicity: way for good user to select when their message handlers get interrupted – Polling: ultimate receive atomicity – never interrupted » Fine as long as user keeps absorbing messages 4/27/2009 cs252-S09, Lecture 24 19 The Fetch Deadlock Problem • Even if a node cannot issue a request, it must sink network transactions! – Incoming transaction may be request generate a response. – Closed system (finite buffering) • Deadlock occurs even if network deadlock free! NETWORK 4/27/2009 cs252-S09, Lecture 24 20 Solutions to Fetch Deadlock? • logically independent request/reply networks – physical networks – virtual channels with separate input/output queues • bound requests and reserve input buffer space – K(P-1) requests + K responses per node – service discipline to avoid fetch deadlock? • NACK on input buffer full – NACK delivery? • Alewife Solution: – Dynamically increase buffer space to memory when necessary – Argument: this is an uncommon case, so use software to fix 4/27/2009 cs252-S09, Lecture 24 21 Example Queue Topology: Alewife • Message-Passing and Shared-Memory both need messages – Thus, can provide both! • When deadlock detected, start storing messages to memory (out of hardware) – Remove deadlock by increasing available queue space • When network starts flowing again, relaunch queued messages – They take loopback path to be handled by local hardware 4/27/2009 cs252-S09, Lecture 24 22 Natural Extensions of Memory System P1 Pn Scale Switch (Interleaved) First-level $ (Interleaved) Main memory P1 Pn $ $ Interconnection network Shared Cache Mem Mem Centralized Memory Dance Hall, UMA Mem Pn P1 $ Mem $ Interconnection network Distributed Memory (NUMA) 4/27/2009 cs252-S09, Lecture 24 23 Sequential Consistency • Memory operations from a proc become visible (to itself and others) in program order • There exists a total order, consistent with this partial order - i.e., an interleaving – the position at which a write occurs in the hypothetical total order should be the same with respect to all processors • Said another way: – For any possible individual run of a program on multiple processors – Should be able to come up with a serial interleaving of all operations that respects » Program Order » Read-after-write orderings (locally and through network) » Also Write-after-read, write-after-write 4/27/2009 cs252-S09, Lecture 24 24 Sequential Consistency Processors P1 issuing memory references as per program order P2 Pn The “sw itch” is randomly set af ter each memory reference Memory • Total order achieved by interleaving accesses from different processes – Maintains program order, and memory operations, from all processes, appear to [issue, execute, complete] atomically w.r.t. others – as if there were no caches, and a single memory • “A multiprocessor is sequentially consistent if the result of any execution is the same as if the operations of all the processors were executed in some sequential order, and the operations of each individual processor appear in this sequence in the order specified by its program.” [Lamport, 1979] 4/27/2009 cs252-S09, Lecture 24 25 Sequential Consistency Example Processor 1 Processor 2 LD1 A LD2 B ST1 A,6 … LD3 A LD4 B ST2 B,13 ST3 B,4 LD5 B … LD6 A ST4 B,21 … LD7 A … LD8 B 4/27/2009 5 7 6 21 One Consistent Serial Order 2 6 6 4 cs252-S09, Lecture 24 LD1 LD2 LD5 ST1 LD6 ST4 LD3 LD4 LD7 ST2 ST3 LD8 A B B A,6 A B,21 A B A B,13 B,4 B 5 7 2 6 6 21 6 4 26 Summary • Many different Message-Passing styles – Global Address space: 2-way – Optimistic message passing: 1-way – Conservative transfer: 3-way • “Fetch Deadlock” – RequestResponse introduces cycle through network – Fix with: » 2 networks » dynamic increase in buffer space • Network Interfaces – User-level access – DMA – Atomicity 4/27/2009 cs252-S09, Lecture 24 27