Transcript KDSM_Ozegovic_v3

Fields
•Digital design
•Computer networks
Staff
•dr. Julije Ozegovic, professor,
•dr. Vesna Pekic, Postdoctoral Research Assistant,
•dr. Ante Kristic, Postdoctoral Research Assistant,
•Marina Prvan, PhD student
Laboratory
•Digital electronic: SSI to LSI applications, Atmel AVR-8,
•Programmable logic: Verilog, Xilinx Spartan3e, CoolRunner II,
•DSP systems: Blackfin 533, 537, Analog Devices ISE,
•Computer networks: LAN, WLAN, routing
obligatory course, 2nd semester of diploma studies (4th year)
advanced knowledge of digital system design using hardware
definition languages (HDL) and complex programmable logic
structures
FPGA and CPLD design
Verilog HDL
•basic syntax
•Logical gate level modeling
•Data flow modeling
•Behavioral modeling
Laboratory:
•Xilinx XC3S500E Spartan-3E (Spartan-3E Starter Kit Board)
•Xilinx CoolRunner-II CPLD (CoolRunner-II Evaluation Board)
•Xilinx ISE WebPack Design Suite
Students’ final projects at the end of the course
Groups of 2-5 students
Projects include:
•CAN controller
•Ethernet interfacing
•RFID reader
•VGA signal generator
•PWM
•Simple game implementation (pong, tetris...)
•SPORT controller
•Audio processing
•LCD controller
Examples of students’ projects
VGA signal generator and tilting maze game
RFID “card” and reader
Examples of students’ projects
image processing
DA/AD conversion and
audio processing
Examples of students’ projects
FFT implementation
simulation results
signal input and output
DSP systems
•DSP system’s architecture and deployment
•Blackfin 533 and 537 DSP processors
•VisualDSP++
•Audio and video processing
•Filter design using MATLAB
•Signal processing in Assembler and C
•Course ends with students’ final projects
Digital electronics
•Boolean algebra and automata theory
•combinatorial and sequential circuits' synthesis
Three main research topics:
•Flow control and QoS assurance
•Wireless computer networks and MAC protocols
•Protocol modeling and simulation
In 2013. and 2014. the research activities of the group
have resulted in three PhD Vivas
Motivation – integration of different kinds of services,
from data to real-time services
TCP is not suitable for the integration with real-time
services
Proposed solution: QoS strategies on access networks
•an alternative flow control (AFC) more suitable for
achieving QoS on the access network has been
suggested
•no changes to the TCP/IP protocol stack on the core
Internet network
•flow control proxy controls the interaction between the
technology used on the access network and on the core
network
•distributed and potentially inexpensive solution
ZATVARANJE POVRATNE
VEZE WTFC
POŠILJATELJA IZA
SPREMNIKA
POSREDNIČKOG
UREĐAJA
TCP POŠILJATELJ S
ALGORITMOM
OGRANIČENJA RASTA
PROZORA ZAGUŠENJA
STANDARDNI WTFC
PRIMATELJ
WTFC
pošiljatelj – primatelj
ZATVARANJE
POVRATNE VEZE
TCP POŠILJATELJA
POSREDNIČKOG
UREĐAJA
TCP
pošiljatelj – primatelj
POSREDNIČKI UREĐAJ
WS
PWR
PTS
TR
WR
PWS
PTR
TS
TCP domena
WTFC domena
ZATVARANJE
POVRATNE VEZE
TCP POŠILJATELJA
NA UDALJENOM
KRAJU
ZAJEDNO S
POVRATNOM
VEZOM WTFC
POŠILJATELJA
POSREDNIČKOG
UREĐAJA
STANDARDNI WTFC
POŠILJATELJ
TCP PRIMATELJ
S OGLAŠAVANJEM PROZORA PRIJEMNIKA
(S ALGORITMOM INDUCIRANOG GUBITKA)
DAVANJE PRIORITETA
RETRANSMITIRANIM
PAKETIMA PRI
PROSLIJEĐIVANJU S
POSREDNIČKOG
UREĐAJA
MAPDV2 jitter with and
without proxy
Model of optimal proxy
between an access network
and core Internet network
Motivation:
•in modern wireless ad-hoc networks, with a high speed
PHY, every collision means a significant loss of useful
bandwidth,
•wireless MAC protocols performance depends on its
parameter values and offers optimal results only in some
network scenarios
•reduction of collision rates - increased protocol
overhead
Goal - to develop protocols that offer low collision rates
while keeping the overhead small, and provide good results
in the various network scenarios
A novel binary contention protocol called binary priority
countdown (BPC) was developed:
•separates priority space from contention codewords
•priority countdown process is not constrained to a
single binary countdown round
•arbitrary medium access priorities can be decremented
through multiple binary countdown
•new optimization and adaptation possibilities
Collision memory effect, occurring in DCF-type networks
and causing throughput decrease, has been detected
•CPCF mechanism, used for limiting this effect, has been
introduced
medij slobodan/period slušanja
BPC medium contention
kodna riječ
0000
kodna riječ
1010
medij zauzet
ne nadmeće se
odustani od nadmetanja
0 0 0 0 1 0
Tx A
ACK
1 0 0
Rx A
PODACI
vrijeme
kodna riječ
0000
1. prijenos podataka
kodna riječ
1100
DIFS
Tx B
RIFS
0 0 0 0 1 1 0 0
SIFS
PODACI
ACK
Rx B
KI
(SKI)
KI
(ZKI)
vrijeme
PRN
Throughput of BPC-DAL and
Simple Binary Countdown
(SBC) compared
Model of network protocol
•provides deeper understanding
•analysis of protocol’s performance
•investigation of optimization possibilities
Goal – development of an accurate model of CPCF
protocol
Method:
•the behavior of a single station is modeled
•the probability τ0 (τ1) that a single station starts to
transmit in a random TS following an idle (busy) timeslot
is obtained
•calculate the saturation throughput for network of n
active stations as a function of τ0 and τ1
Markov chain for the
single backoff stage
Network throughput obtained
from model and simulations
compared
Recent publications
•I. Kedzo, J. Ozegovic, and A. Kristic, “BPC – A binary priority
countdown protocol,” Ad Hoc Networks, vol. 11, no. 3, pp. 747–
764, May 2013.
•A. Kristic, J. Ozegovic, and I. Kedzo, “Mathematical model of
Constrained Priority Countdown Freezing Protocol,” SoftCOM
2014, Split, Croatia
•A. Kristic, J. Ozegovic, and I. Kedzo, “Mathematical model of
simplified Constrained Priority Countdown Freezing protocol,”
ISCC 2013, Split, Croatia
•I. Kedzo, J. Ozegovic, and A. Kristic, “Contention overhead —
adaptive binary priority countdown protocol,” SoftCOM 2013,
Primosten, Croatia
Recent publications
•A. Kristic, J. Ozegovic, and I. Kedzo, “Improved mathematical
model of simplified Constrained Priority Countdown Freezing
protocol,” SoftCOM 2013, Primosten, Croatia
•V. Pekic, J. Ozegovic, and I. Kedzo, “Adaptive Algorithm for WTFC
to TCP Flow Control Proxy,” SoftCOM 2012, Split, Croatia
•I. Kedzo, J. Ozegovic, and A. Kristic, “Collision rate adaptive
binary priority countdown protocol,” SoftCOM 2012, Split, Croatia
•V. Pekic, A. Kristic, and J. Ozegovic, “WTFC to TCP flow control
proxy,” ACCESS 2012, Split, Croatia
•I. Kedzo, J. Ozegovic, and V. Pekic, “Constrained Priority
Countdown Freezing - A Collision Memory Avoidance Algorithm,”
ICWMC 2012, Venice, Italy
Possible fields of cooperation
•Network online throughput modeling (Ante, Marina)
•Matlab simulations
•Network offline throughput modeling (Vesna, Ante)
•NS2 simulations
•FPGA architecture and throughput modeling (Julije,
Marina)
•Automata models
ALICE O2 simulation
•Installed OMNeT++ 4.4.1 and INET framework
•Getting familiar with NED language and existing C++
classes hierarchy
•Studying Charles’ code
•Trying to recreate the same results
Surveying the literature
General:
•TDR for the upgrade of the O2 system, Aug. 2014.
•Upgrade of ALICE - letter of intent, Sept. 2012.
•The ALICE data acquisition system, Nuclear Instruments and
Methods in Physics Research A, 2014.
•ALICE Upgrade Program, David Silvermyr, ORNL, 2014.
•…
Front end electronics and readout
•Existing FEC cards
•PASA, ALTRO, super-ALTRO
•New SAMPA card?
Surveying the literature
Clustering and tracking
•Design of a Hardware Track Finder (Fast Tracker) for the
ATLAS Trigger, ATL-DAQ-PROC, 2013
•A multi-core FPGA-based 2D-clustering algorithm for highthroughput data intensive applications, ATL-DAQ-PROC,
2013
•A multi-core FPGA-based clustering algorithm for real-time
image processing, NSS/MIC, 2013.
•Platform benchmarking with a cluster finder algorithm for
the ALICE upgrade, Sylvain Chapeland, 2014.
•…
FLP:
•The O2 Simulation program, by Charles 29/08/2014
Questions arising:
•Network online throughput modeling (Ante, Vesna)
•Omnet simulations: check and extend Charle's code
•Matlab simulations - decide to use it or not
•FPGA architecture and throughput modeling (Julije,
Marina)
•Learn more about FLP architecture
•Create more detailed model
•Include in Omnet simulation
•Automata models - decide to use or not