Transcript FPX KCPSM Module

The FPX KCPSM Module:
An Embedded, Reconfigurable Active
Processing Module for the FPX
Henry Fu
Washington University
Applied Research Lab
Supported by: NSF ANI-0096052
and Xilinx Corp.
http://www.arl.wustl.edu/arl/projects/fpx/fpx_kcpsm/
[email protected]
The FPX KCPSM Module
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Motivation
• Hardware plugins are well suited for
processing data with high throughput
• Software plugins are well suited for
implementing complex control functions
 Need a hybrid plugins that can implement
complex control functions with high data
throughput
The FPX KCPSM Module
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Introduction
• The FPX KCPSM module is a hardware plugin
that executes software on an embedded softcore processor
• It implements active networking functions on
the FPX using both hardware and software
• It includes circuits to be reprogrammed over
the network and to execute new programs
between the processing of data packets
The FPX KCPSM Module
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Overview
• The FPX KCPSM Module is composed of
three parts:
– The KCPSM, a 8-bit microprocessor developed
by Xilinx Corp.
– The Protocol Wrappers, a circuit used to
simplify the processing of ATM cells, AAL5
frames, IP packets, and UDP datagrams
– The Interface, a circuit used to interconnect the
KCPSM and the Protocol Wrappers
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The FPX KCPSM Module
KCPSM
DATA
PROGRAM
MEMORY
DATA
BUS
ADDR
D_MOD_IN
INST
D_OUT_MOD
INTERFACE
SOC_MOD_IN
TCA_MOD_IN
INST
CONTROL
SIGNALS
ATM CELLS
ADDR
MEMORY
ADDR
D_MOD_IN
I/O
BUS
UDP PACKETS
UDP PACKETS
ATM CELLS
PORT_ID
D_OUT_MOD
SOC_OUT_MOD
CONTROL
SIGNALS
TCA_OUT_MOD
PROTOCOL WRAPPERS
CLK
RESET_L
ENABLE_L
The FPX KCPSM Module
READY_L
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Features
• Software can be loaded over the network
through the use of UDP datagrams
• Up to four data packets and up to two
programs can be stored in the module at a
time
 The processing function can be changed
dynamically, on a packet by packet basis
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Background of the FPX
• The FPX (Field Programmable Port Extender)
– A reprogrammable logic device that provides a
hardware platform to deploy network modules
– It is composed of two parts:
• NID (Network Interface Device), a circuit that
interconnects the WUGS (Washington University
Gigabit Switch), the line cards, and the RAD
• RAD (Reprogrammable Application Device), a circuit
that can be reprogrammed to hold user-defined
network modules
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Configuration of the FPX
• The FPX acts as an interface between the line
cards and the WUGS
Line
Card
OC3/
OC12/
OC48
FPX
Fieldprogrammable
Port
Extender
IPP
OPP
IPP
OPP
Gigabit
Switch
Fabric
Line
Card
OC3/
OC12/
OC48
The FPX KCPSM Module
FPX
Fieldprogrammable
Port
Extender
IPP
OPP
IPP
OPP
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Major Components of the FPX
SDRAM
Loopback
Data
SRAM
Module
Data
Module
Data
SDRAM
KCPSM
Data
SRAM
RAD
VC
VC
RAD
Program
SRAM
VC
EC
EC
Switch
The FPX KCPSM Module
VC
NID
FPX
LineCard
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Background of the KCPSM
• The KCPSM (Constant (K) Coded
Programmable State Machine)
– A 8-bit microcontroller
– Consumes only 35 CLBs in FPGA
– Provides 49 different instructions, 16 registers,
256 directly and indirectly addressable ports,
and a maskable interrupt
– Runs at a maximum frequency of 70 MHz
– Developed by Ken Chapman of Xilinx Corp.
The FPX KCPSM Module
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Background of the KCPSM (More)
• The KCPSM
– Designed for Xilinx Virtex and Spart-II devices
– Provided in the form of an EDIF macro
– Included an assembler and debugger
INPUT [7:0]
OUTPUT [7:0]
INTERRUPT
PORT_ID [7:0]
KCPSM
CLK
INST [15:0]
The FPX KCPSM Module
READ_STROBE
WRITE_STROBE
ADDR [7:0]
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Downloading the KCPSM Package
• The KCPSM Package from Xilinx Corp.
– Visit
• http://www.arl.wustl.edu/arl/projects/fpx/fpx_kcpsm
– Left click on the KCPSM package
– Open the ZIP file
– Extract to h:\xilinx
– Start Cygwin Bash Shell
• Engineering > FPGA Tools > Cygwin Bash Shell
• cd /cygdrive/h/xilinx/
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Contents of the KCPSM Package
• Access the KCPSM Package
– An assembler called KCPSMBLE
• ./KCPSMBLE debug.psm
– An debugger called PSMDEBUG
• ./PSMDEBUG debug.coe
– Documentations
• A modified KCPSM package that includes
example programs will be included as part of
the FPX KCPSM package during the exercise
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Background of the Protocol Wrappers
• The Protocol Wrappers
– A circuit that streamline the networking
functions to process ATM cells, AAL5 frames,
IP packets, and UDP datagrams
– A layered design that consists different
processing circuit in each layer
– Allows application to be implemented at a level
where important details are exposed and
irrelevant details are hidden
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Overview of the Protocol Wrappers
• The Protocol Wrappers is composed of four
circuits:
– Cell Processor processes raw ATM cells
between network interfaces
– Frame Processor processes variable length
AAL5 frames
– IP Processor processes IP packets
– UDP Processor sends and receives UDP
datagrams
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Overview of the Protocol Wrappers (More)
Interfaces to Off-Chip Memories
Application-level
Hardware Module
Data
Input
Data
Output
UDP Processor
IP Processor
Frame Processor
Cell Processor
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Downloading the Wrappers Package
• The Protocol Wrappers Package
– Visit
• http://www.arl.wustl.edu/arl/projects/fpx/fpx_kcpsm
– Right click on the Wrappers Package
– Save it to h:\
– Start Cygwin Bash Shell
•
•
•
•
Engineering > FPGA Tools > Cygwin Bash Shell
cd /cygdrive/h/
gunzip wrappers.tar.gz
tar xvf wrappers.tar
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Contents of the Protocol Wrappers Package
• Access the Protocol Wrappers Package
– Cell Processor
• cellwrapper.vhdl, the VHDL instantiation file
• cellproc_sim.vhd, the VHDL simulation file
• cellproc.edn, the EDIF Macro synthesis file
– Frame Processor
• framewrapper.vhdl, the VHDL instantiation file
• frameproc_sim.vhd, the VHDL simulation file
• frameproc.edn, the EDIF Macro synthesis file
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Contents of the Protocol Wrappers Package
– IP Processor
• ipwrapper.vhdl, the VHDL instantiation file
• ipproc_sim.vhd, the VHDL simulation file
• ipproc.edn, the EDIF Macro synthesis file
– UDP Processor
• udpwrapper.vhdl, the VHDL instantiation file
• udpproc_sim.vhd, the VHDL simulation file
• udpproc.edn, the EDIF Macro synthesis file
– COREGEN Components
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Overview of the Interface
• The Interface
– A circuit that interconnects the KCPSM and the
Protocol Wrappers
– Switches the source and destination IP address
and UDP port numbers, buffers the incoming
UDP packets and stores them to the memory,
resets the KCPSM, and writes the outgoing
UDP packets back to the sender
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Overview of the Interface (More)
• The Interface is composed of seven control
units:
– UDP Packets Header Switch
– UDP Packets FIFO Control
– UDP Packets Type Check
– UDP Packets Store Control
– KCPSM Reset Control
– Unmodified Program Packets Echo Control
– Completed Data Packets Write Control
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Overview of the Interface (More)
KCPSM
Control
Signals
ADDR
KCPSM
Reset Control
INST
Program
Memory
ADDR DATA
Control
Signals
Data
Memory
Completed
Data
Packet
UDP Packets
FIFO Control
UDP
Packet
UDP
Packet
Control
Signals
UDP Packets
Header Switch
UDP
Packet
FIFO
UDP Packets
Type Check
The FPX KCPSM Module
Program Data
Packet
Packet
Buffered
UDP
Packet
Data Packets
Write Control
Write
Grant
UDP Packets
Store Control
Control
Signals
UDP
Packet
Unmodified
Program
Packet
Program Pkts
Echo Control
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Overview of the Interface (More)
KCPSM
Control
Signals
ADDR
KCPSM
Reset Control
INST
Program
Memory
ADDR DATA
Control
Signals
Data
Memory
Completed
Data
Packet
UDP Packets
FIFO Control
UDP
Packet
UDP
Packet
Control
Signals
UDP Packets
Header Switch
UDP
Packet
FIFO
UDP Packets
Type Check
The FPX KCPSM Module
Program Data
Packet
Packet
Buffered
UDP
Packet
Data Packets
Write Control
Write
Grant
UDP Packets
Store Control
Control
Signals
UDP
Packet
Unmodified
Program
Packet
Program Pkts
Echo Control
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UDP Packets Header Switch Control
• UDP Packets Header Switch Control
– Switches the source and destination IP address
and UDP Port numbers of the UDP packets
– Allows the unmodified program packets and
completed data packets to be echoed back to
the sender
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UDP Packets FIFO Control
• UDP Packets FIFO Control
– Buffers incoming UDP packets
– Delays the arrival of the UDP packets to the
UDP Packets Store Control so that it can wait
for the result from the UDP Packet Type Check
in order to determine whether to store the UDP
packets into the program memory or into the
data memory
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UDP Packets Type Check
• UDP Packets Type Check
– Determines if the incoming UDP packets is a
program packet or a data packet
– Inspects the first word of the UDP payload
– 0x00000000 indicates a program packet
– 0x00000001 indicates a data packet
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UDP Packets Store Control
• UDP Packets Store Control
– If the incoming packet is a program packet
• Stores the UDP payload, except the first word, into
the program memory
– If the incoming packet is a data packet
• Stores the whole packets, including the ATM, AAL5
Frame, IP and UDP headers, the UDP payload, and
the ATM trailers into the data memory
– Increments the bank counters so that the next
UDP packet will store into the next available
bank of memory
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KCPSM Reset Control
• KCPSM Reset Control
– Resets the KCPSM by asserting the Interrupt
input of the KCPSM for two clock cycles
– If there is no new program loaded
• Resets the KCPSM so that it processes the next
available data packets using the current program
– If there is a new program loaded
• Resets the KCPSM and increments the program
counter so that it processes the next available data
packets using the new program
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Unmodified Program Packets Echo Control
• Unmodified Program Packets Echo Control
– Echoes the incoming program packets back to
the sender
– Passes any non-UDP packets through the
module
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Completed Data Packets Write Control
• Completed Data Packets Write Control
– Writes the completed data packets back to the
sender only if
• they have been processed by the KCPSM
• there is no new incoming data packet by inspecting
the WR_GRANT signal from the UDP Packets Store
Control
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The FPX KCPSM Module Demo
• Network Data Compression using RLE (RunLength Encoding) Algorithm
– Compression example:
• ‘AAAABBBC’ compresses to ‘A4B3C’
– Decompression example:
• ‘A4B3C’ decompresses to ‘AAAABBBC’
– Allowed input characters range from ‘A’ to ‘Z’,
‘a’ to ‘z’
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The FPX KCPSM Module Demo (More)
• Log on to fpx.arl.wustl.edu / fpx2.arl.wustl.edu
using SSH (Secure Shell)
• fpx / fpx2 is connected to the line cards / fpx
boards / WUGS
• fpx / fpx2 directs network traffic to the line
cards / fpx boards / WUGS
• IP over ATM is configured on fpx / fpx2 to send
UDP packets on VCI / VPI #96
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The FPX KCPSM Module Demo (More)
• A C program called UDPTEST is executed on
the fpx / fpx2 and is used to send program
packets to the FPX KCPSM module
– Download URL:
• http://www.arl.wustl.edu/arl/projects/fpx/fpx_kcpsm/
– Usage:
• ./UDPTEST RLEEN.TBP (Encoder)
• ./UDPTEST RLEDE.TBP (Decoder)
– The <FILENAME.TBP> file contains the raw
machine code of the KCPSM program
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Program Packet Processing
Independent
Process
KCPSM
ADDR
Proceed as long as
there is new incoming
program packet
Program Packet
The FPX KCPSM Module
INST
ALTERNATE
BANK
CURRENT
BANK
PROGRAM
MEMORY
ADDR
INST
INTERFACE
Proceed as long as
there is new incoming
program packet
Program Packet
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The FPX KCPSM Module Demo (More)
• A C program called UDPSTR is executed on
the fpx / fpx2 and is used to send data packets
containing character strings to the FPX
KCPSM module
– Download URL:
• http://www.arl.wustl.edu/arl/projects/fpx/fpx_kcpsm/
– Usage:
• ./UDPSTR [-h hostname] [-p destination port]
– Enter the character strings in the input prompt
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Data Packet Processing
Proceed as long as
there is data packet
KCPSM
ADDR
I/O
BUS
ALT
ALT
ALT
CUR
BANK BANK BANK BANK
Proceed as long as
there is new
incoming data packet
DA
ADDR
Data Packet
The FPX KCPSM Module
TA
DATA
BUS
MEM ORY
ADDR
INTERFACE
DATA
BUS
Proceed as long as
there is completed data packet
and no new incoming data packet
Data Packet
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The FPX KCPSM Module (Demo)
• Screenshot of the compression example:
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The FPX KCPSM Module Demo (More)
• Screenshot of the decompression example:
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Synthesis Results
• The FPX KCPSM Module is synthesized to a
Xilinx XCV1000E-7-FG680:
– Maximum Frequency: 70 MHz
– Chip Utilization: 35% (4305 / 12288 slices)
– External Input Buffers: 69 uses
– External Output Buffers: 105 uses
– Total LUTS: 3807 uses
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Synthesis Results (More)
• The Xinlinx backend synthesis script:
– ngdbuild -p xcv1000e-7-fg680 -uc design.ucf
– map -p xcv1000e-7-fg680 -o top.ncd design.ngd
design.pcf
– par -w -ol 2 top.ncd design.ncd design.pcf
– trce design.ncd design.pcf -e 3 -o design.twr -xml
design_trce.xml
– bitgen design.ncd -b -l -w -f bitgen.ut
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Conclusion
• The FPX KCPSM Module
– Demonstrates how to embed a softcore
processor and how to use the Protocol
Wrappers in an FPX module
– Combines software flexibility and hardware
performance into a hybrid module
– Targets to work with the KCPSM, WUGS, FPX
research environment, but can easily be
changed to work with any FPGA-based system
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