Transcript Comparison b/w Electrical and Optical communication inside Chip

COMPARISON B/W ELECTRICAL AND
OPTICAL COMMUNICATION INSIDE CHIP
Irfan Ullah
Department of Information and Communication Engineering
Myongji university, Yongin, South Korea
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Computer Bus
“Subsystem that transfers data between
components inside a computer”
•First generation
• Bundles of wire
•Second generation
• CPU and memory on one side
•Third generation
• HyperTransport “Lightning Data Transport
(LDT)”
•
•
25.6 GB/s unidirectional
InfiniBand “Switched fabric communications link”
•
Fibre Channel, PCI Express, Serial ATA (SATA)
Core-to-core Communication
Message passing
“form of communication used in parallel computing,
object-oriented programming, and interprocess
communication”
•Less PCB ~ more data rate ~ less loss
Backside Bus
“connects the CPU to CPU
cache memory”
Cache reduces the average
time to access memory
Electrical communication inside SOC
 Bus topology
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•
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Shared bus “Masters and slaves connected to a shared bus”
Hierarchical bus “Shared buses interconnected by bridges”
Ring “Master and slave communicated using a ring interface”
 Bus approach
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AMBA (Advanced Microcontroller Bus Architecture) by ARM
Altera by AVALON
CORECONNECT by IBM
WISHBONE by Silicore Corporation’s
VCI (Virtual Component Interface) by VSIA
Sinics OCP (Open Core Protocol) by OCP
Cont’d..

Single on-chip bus can not address the needs of all SoCs
 Unsuccessful due to
• Commercial issues
• Every application needs its own architecture
Published in 2000
Published in 1985
Cont’d..
H.264 digital video decoder
For SOC remapping
published in 1999
Texas Instruments
Ad-hoc approach
SOC Bus
•
Processing cores on a single chip
• On-chip interconnection networks are
mostly implemented using buses
• Bus base networks
• AMBA, Avalon, CoreConnect, STBus,
Wishbone, etc...
• Characteristics using bus
• Topology
• Arbitration method
• bus-width
• Types of data transfers
“The performance of the
SoC design heavily depends
upon the efficiency of its bus
structure”
PI (Peripheral Interconnect) bus
•
•
Used in highly integrated SoC designs
Bus agents are on-chip modules
OCP (Open Core Protocol)
•
Interconnects IP cores to on-chip bus
SOC Bus
Optical fiber communication application
Fastest system
Multi-core
Today
• A few large cores on each chip
• Diminishing returns prevent
cores from getting more
complex
• Only option for future scaling is
to add more cores
Tomorrow
• Simple cores are more power and
area efficient
• Global structures do not scale; all
resources must be distributed
m
p
m
p
p
switch
m
c
m
p
switch
m
p
c
m
m
m
L2 Cache
m
switch
m
p
switch
p
switch
m
p
switch
p
m
m
p
m
switch
p
switch
switch
p
switch
p
p
switch
p
switch
BUS
m
p
m
p
switch
switch
p
switch
switch
Cont’d..
• Scalability
• How do we turn additional cores into additional performance?
• Must accelerate single apps, not just run more apps in parallel
• Efficient core-to-core communication is crucial
• Architectures that grow easily with each new technology generation
• Programming
• Traditional parallel programming techniques are hard
• Parallel machines were rare and used only by rocket scientists
• Multicores are ubiquitous and must be programmable by anyone
• Power
• Already a first-order design constraint
• More cores and more communication  more power
• Previous tricks (e.g. lower Vdd) are running out of steam
Electrical communication based cores
Bus-based Interconnect
p
p
c
c
BUS
L2 Cache
DRAM
• Single shared resource
• Uniform communication cost
• Communication through
memory
• Doesn’t scale to many cores
due to contention and long
wires
• Scalable up to about 8 cores
Point-to-Point Mesh Network
p
m
p
switch
m
p
switch
m
p
p
p
m
m
m
switch
switch
m
p
p
switch
• More energy efficient than bus
• Scalable to hundreds of cores
p
switch
m
DRAM
DRAM
m
switch
p
switch
switch
p
m
p
p
switch
p
switch
switch
m
switch
p
p
switch
m
switch
m
m
switch
DRAM
m
DRAM
m
Programming
• Meshes and small cores solve the physical scaling
challenge, but programming remains a barrier
• Parallelizing applications to thousands of cores is hard
• For high performance, communication and locality must be
managed
Observations:
• A cheap broadcast communication mechanism can make
programming easier
• On-chip optical components enable cheap, energy-efficient
broadcast
Optical connection
Electrical Mesh Interconnect
m
m
p
m
p
switch
m
p
switch
m
p
m
switch
p
m
switch
p
m
m
switch
p
switch
m
p
switch
switch
p
m
p
p
m
switch
switch
m
switch
p
p
switch
p
m
m
m
p
switch
switch
p
switch
switch
Optical Broadcast WDM Interconnect
18
Cont’d..
• Signal through every core
• Signal reaches all cores in <2ns
optical waveguide
Cont’d..
N
cores
20
Cont’d..
 Each core sends data using a different wavelength  no contention
 Data is sent once, any or all cores can receive it  efficient broadcast
multi-wavelength source waveguide
modulator
data waveguide
modulator
driver
filter
transimpedance
amplifier
photodetector
flip-flop
sending core
flip-flop
receiving core
21
Cont’d..
 Each core contains receive filters and a FIFO buffer for every sender
 Data is buffered at receiver until needed by the processing core
 Receiver can screen data by sender (i.e. wavelength) or message type
32
Processor
Core
Processor
Core
sending core A sending core B
FIFO
32
FIFO
32
FIFO
FIFO
FIFO
FIFO
32
Processor Core
receiving core
Cont’d..
 64 cores, 32 lines, 1 Gb/s
 Transmit BW: 64 cores x 1 Gb/s x 32 lines = 2
Tb/s
 Receive-Weighted BW: 2 Tb/s * 63 receivers =
126 Tb/s
Mechanism
Research by INTEL
50Gbps Silicon Photonics link
Cont’d..
Cont’d..
50Gbps Silicon Photonics link
IBM Research
Cont’d..
Cont’d..
IBM optical communication inside chip
Links
Length
BW
Power
~100 k
~1 cm
~1 Tbps
<10mW
Cont’d..
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•
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CMOS-Integrated optical nanophotonics
Intra-chip optical network (ICON)
“Transmission of data using pulses of light
instead of electrical signals”
Electrical and optical devices on the same
piece of silicon
Smaller, faster and more power-efficient
chips
Silicon nanophotonics
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•
•
•
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WDM
Light sources
Modulators
Switches
Detectors
Cont’d..
Links
Length
BW
Power
~100 k
~0.1-0.3 cm
~1 Tbps
<1mW
Optical network for 64-core
Cont’d..