Transcript Untersuchungen zur MAC Address Translation (MAT)

A Simplified, Cost-Effective
MPLS Labeling Architecture for
Access Networks
Harald Widiger1, Stephan Kubisch1, Daniel Duchow1, Thomas
Bahls2, Dirk Timmermann1
1University
of Rostock, Germany
2Siemens Communications, Greifswald, Germany
Outline
Access Network Architecture
Multi Protocol Label Switching
The MPLS-User Network Interface
Implementation and Simulation
Results
 Conclusion




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Access Network Environment
User
Linecards
1
.
.
.
Broadband
Access Server
Central Switching
Unit
DSL/
Ethernet
1
.
.
.
MPLSUNI
Gigabit
Ethernet
Core-Network of
Internet Service
Provider
Multiple
Gigabit
Ethernet
n
m
 Need for Differential Services, increased QoS
 Derived from Information within each Frame
 MPLS-UNI to create space for information
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Multi Protocol Label Switching
(MPLS)
Ingress Point
LER
LSR
LSR
LSR
LSR
LER
Egress Point
LSR
LSR
LER
 Path of a Frame
through an MPLS
switched Network
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 Encapsulation
Scheme
 Meant for fast
routing purposes
 Here: Simply a
container to carry
information
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MPLS-Encapsulation
Customer Provider
Side Side
DST MAC
SRC MAC
DST MAC
SRC MAC
Upstream
Ethertype (MPLS)
MPLS Label Stack
VLAN
DST MAC
Ethertype
SRC MAC
Data & Padding
FCS
Downstream
VLAN
Tunnel Label
Tunnel Label
T Label
EXP
TTL
VC Label
VC Label
VC Label
EXP
TTL
B
B
Label 1
Label 0
Ethertype
Data & Padding
FCS
 MPLS Label Stack usually between layer 2
and layer 3 header
 We use encapsulation scheme by Martini
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MPLS-User Network Interface
(MPLS-UNI)
 MPLS Label Stack container to carry
information
 No complete LER implementation with an
LDP running is necessary
 Possibility to implement the whole system in
Hardware
 Primary Functionality:
 Upstream direction insert an MPLS Label Stack
 Downstream direction  remove MPLS Label
Stacks
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MPLS-UNI Architecture
Memory
CPU
Interface
Memory
Arbiter
Key Parser /
Framebuffer
MPLS Delabeler
MPLS Delabeler
MPLS Delabeler
MPLS Delabeler
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MPLS Labeler
MPLS Labeler
MPLS Labeler
MPLS Labeler
Framebuffer
Framebuffer
Framebuffer
Framebuffer
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Framebuffer with Key Parser
SRC MAC
Key
DST MAC
VLAN 1
VLAN 2
Deadline
Key
Write
FSM
Keybuffer
(DP RAM)
Stored
Frames
Ethertype
SRC IP
DST IP
Comp
Time
Frame
Write
FSM
Framebuffer
(DP RAM)
Buffer
Usage
Data
DSCP
Read
FSM
Data Out
Data In
 Stores frames and parsed keys
 Key is configurable at time of compilation

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Reduction of required hardware resources in the MPLS-UNI
itself
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Memory Arbitration
Memory
Key, ID
Mem Data, ID
Key 0
Functionality 0
Memory
Arbitration
Key 3
Key
Deadline
Key
Mod 0
Key ID
DeMultiplexer
Functionality 3
Comp
Time
Slack 0
Key
Deadline
Comp
Time
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Key
Mod 3
LLF
Sheduler
Slack 3
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Implementation Results
(Xilinx Virtex 4 FX20-11)
Hardware Module
Speed in MHz
MPLS-UNI
Area
Logic
min/typ/max
BRAMs
1125/1486/2227
11/11/12
MPLS-Labeler
187
129
2
MPLS-Delabeler
322
101
0
Memory Arbiter
163
152/203/343
0
CPU Arbiter
168
640
0
Key Parser & Framebuffer
159
352/494/721
9/9/10
Framebuffer
177
205
0
Memory internal (1K Entries)
126
783/1145/1917
3/7/15
Sync FIFOs + MACs
169
850
6
∑System
130
2600/3400/4700
20/24/33
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Performance
 4 Gbps @
„natural Traffic“
60




4096 Keys
50
Loss Rate in %
2048 Keys
40
512 Keys
30
8192 Keys
20
10
0
60
70
80
90
100
110
Size of the Frames
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120
130
140
150
30
10
11
49
%
%
%
%
60 Byte
590 Byte
1514 Byte
random
 No packet loss
 Average delay of
120 Cycles 
860 ns @125
MHz
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Conclusion
 Powerful and cost-effective solution to
expand MPLS networks into the
Access Network area
 @125 MHz, 4 Gbps can be handled
 Size of the system can be minimized
considering the actual tasks
 Functional spectrum can be
broadened, due to reconfigurable HW
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