Transcript sheets
Sonics Bus Modeling for Felix/VCC EE249 Project Presentation December 3, 1999 Mike Sheets Introduction What is involved in a bus model? Sonics two level arbitration scheme Modeling the arbiter in VCC Performance simulation Problems with the model December 3, 1999 Modeling Sonics in Felix/VCC 2 Modeling in Felix/VCC Architecture exploration requires mapping behavior onto architecture SiliconBackplane is fundamentally a bus Bus models are fundamentally arbitration models Can model Sonics architecture by adding a new arbiter to VCC December 3, 1999 Modeling Sonics in Felix/VCC 3 TDMA Arbitration slot (time slice) 0 1 2 3 4 5 … n-1 0 1 2 3 … frame (length n) Time Division Multiple Access Each slot is allocated to at most one transmitter Each slot has a fixed time duration Each frame contains n slots Frame repeats continuously December 3, 1999 Modeling Sonics in Felix/VCC 4 Token Passing Arbitration 0 n-1 1 … 2 current token owner 3 Token Passing Arbitration (Round Robin) Token is passed in a predefined order Transmitter can only send when has token When finished transmitting, passes token on December 3, 1999 Modeling Sonics in Felix/VCC 5 Bus Arbitration Scheme Reliability TDMA Round-robin (token passing) Flexibility December 3, 1999 Fixed slots Guaranteed bandwidth Potentially wasteful Tokens Guaranteed fair, but might slow down fast initiators Slot allocated when needed Modeling Sonics in Felix/VCC 6 Sonics Hybrid Arbitration Scheme Implemented as two tiers, slice (TDMA) and token (round robin) Owner of the slice gets right of refusal If owner not ready to send, uses token arbiter Can trade-off between slice, token, and both to balance reliability and flexibility December 3, 1999 Modeling Sonics in Felix/VCC 7 Sonics Bus Model Arbiter IClk SBClk Initiator Core Processor Initiator Agent OCP Pipelined commands Posted writes Selectable read latency TClk OCP Clock synch., SB handshaking Sonics SiliconBackplane Target Core Memory, I/O ports Receiver Flexible bandwidth arbitration model Target Agent Interconnect Clock synch., SB handshaking Sender SBClk TDMA slot map gives slot owner right of refusal Unowned/unused slots fall to round-robin arbitration SBClk typically different from IClk and TClk so synchronization required Latency after slice granted is user-specified between 2-7 SBClk cycles December 3, 1999 Modeling Sonics in Felix/VCC 8 Sonics Architecture December 3, 1999 Cores conform to Open Core Protocol (OCP) SiliconBackplane is synthesized by Sonics tools Modeling Sonics in Felix/VCC 9 Behavioral Model December 3, 1999 Four initiator agents and four target agents in a daisy-chain Initiator agent access patterns are uniform pulse trains Target agents simply sink the data Modeling Sonics in Felix/VCC 10 Hardware Mapping December 3, 1999 TestCores mapped to hardware cores Communication mapped to SiliconBackplane Modeling Sonics in Felix/VCC 11 Arbitration Model in VCC Sender 1) Posted write 2) Submit transaction Behaviors run continuously CTA 4) Receive data Receiver instantaneous December 3, 1999 Arbiter 3) Complete transaction time delay Modeling Sonics in Felix/VCC 12 Communication Delay Model 1. 2. 3. 4. 5. Receive a bus transaction Synchronize request to SiliconBackplane clock Arbitrate multiple simultaneous requests to determine the correct time slice Add SiliconBackplane pipeline delays Notify communication complete December 3, 1999 Modeling Sonics in Felix/VCC 13 Sonics Arbiter Parameters Bus parameters TDMA time-wheel counter maximums Token-passing order Bus frequency Initiator parameters (communication link) Arbitration policy (slice, token, both) TDMA look-up table (slot map) Minimum number of slots between requests December 3, 1999 Modeling Sonics in Felix/VCC 14 Simulation Results Gantt charts show access pattern Legend December 3, 1999 Modeling Sonics in Felix/VCC 15 Simulation Results (2) Statistics are provided in tabular form Bus utilization (total or per initiator) Arbitration mean latency (total or per initiator) Most/least utilized connection Results used to tweak arbitration parameters Arbitration policy, slot map, token ordering Bus frequency December 3, 1999 Modeling Sonics in Felix/VCC 16 Queuing Receiver Communication Posted write Sender CTA Arbiter Data available Receiver Acknowledge Queue Posted writes can come at any rate handshake Can be implemented using behavior framework Code generation for queue Estimation for queue December 3, 1999 Modeling Sonics in Felix/VCC 17 Queuing Sender Communication Sender Queue Need a handshake here, but the required signals are not available CTA Arbiter Receiver Posted writes can come at any rate Output queue behavior cannot be implemented using any current VCC framework Can fake it by adding CTA queues inside arbiter Problem is being addressed in a future version of VCC December 3, 1999 Modeling Sonics in Felix/VCC 18 Summary Sonics SiliconBackplane can be implemented as an arbiter model in VCC Mapping communication to the arbiter model yields useful bus utilization statistics Model is cycle accurate, but made fast by skipping unimportant cycles Queuing model in VCC has some problems December 3, 1999 Modeling Sonics in Felix/VCC 19