Transcript TYPE TITLE IN ALL CAPS

Hall D Online Meeting
28 March 2008
Fast Electronics
R. Chris Cuevas
Group Leader
Jefferson Lab
Experimental Nuclear Physics Division
System Engineering - Update
-- Level 1 Trigger drawings/documentation
The simple view
Overall system diagrams:
Front End crate configuration
Network diagrams
Fiber optic distribution
-- Module specification documents
FADC250
FADC125
F1TDC
Crate Trigger Processor (CTP)
Signal Distribution (SD)
Trigger Interface (TI)
SubSystem Processor (SSP)
Global Trigger Processor (GTP)
Trigger Supervisor (TS)
Trigger Distributor (TD)
Front End Electronics & Level 1 Trigger Modules
Fiber Optic
Clock/Trigger
Distribution
Detector
Signals
(12)
(1)
Clock
Crate Trigger Processor
Fiber Optic
Distribution
(# Boards)
- (~400) FADC250
- (~140) F1TDC
- (<40) Crate Trigger Processor
(8)
(2)
- (~80) Trigger Interface
- (~80) Signal Distribution
Cuevas Updated 28MARCH08
** Standard VXS Crate
Implement GTP on two Switch Slots
More updates,,
• 26 weeks until the end of FY08
• Identified FY09 PED activities have started:
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FADC250 – Initial batch of 5 modules have been tested (We will have 9 units by end of April)
4 more prototype modules are out for assembly
Front panels; heat sink fabrication
Firmware has been completed! Fully tested on 3 of 5 modules. (Initial units)
Test new modules after they are fully assembled in the ‘test stand’.
Two new Wiener 20 Slot VXS crates – (Abhishek, Ben, Hai, Chris, Jeff)
Received and measurements of slot to slot skew have been recorded.
Need to complete power supply ripple testing etc.
Trigger Interface – ( Ed, Ben, Jeff )
Schematic complete. Draft specification distributed.
Final layout and check is in progress
Board quotation received and parts have been ordered
Signal Distribution module – Abhishek, et al
Draft specification updated from meeting discussions. Need to distribute for comments
Components selected and schematics have been started
Details of programming this module are evolving
More updates,,
F1TDC Version 2 – Create new specifications and functional requirement document (Fernando, Ed)
This activity will start later in the year
Crate Trigger Processor – Design and prototype circuit board for full crate (Hai, Jeff, Ben, Chris)
Specification has been generated and distributed
Xilinx Virtex 5 parts have been ordered. Other parts will need to be ordered soon.
Schematics are complete and are being checked.
Layout to begin after Trigger Interface is complete
Simulation of FX20 to LX50T (Virtex 4 to Virtex 5) Gigabit Transceivers has been started
Microcontroller development tools ordered and will begin design soon
SubSystem Processor – (Ben)
Initial specification was named ESP and the function descriptions of this module have not changed
Document needs to be ‘formatted’ for review, and key functions presented at the May review.
Global Trigger Processor – Dave Doughty, et al
NEED Draft specification and functional description document
Good information gathered at recent Trigger Workshop
Trigger Supervisor – (Ed) NEED Draft specification and functional description document
Trigger Distributor(s) – (Ed, Ben) Description discussed at Trigger Workshop
Draft specification and functional description needed
More updates,,
•
Detailed System Drawings – Updated regularly (Chris, Mark)
Level of detail is progressing well
Fiber optic hardware specified and budgetary estimates requested
Start converting the logical drawings to detailed rack drawings
Items that need more work and details: (Probably more )
1.
FADC250 Level 1 trigger processing functions
Energy Sum function complete
Hit Bit processing functions – needs documentation ( Tagger )
Track Count processing function - needs documentation (TOF, SC )
2.
Level 1 Trigger Timing Diagram
The latency and propagation delays for transferring the L1 digital data
from board to board, crate to crate, processing, and then distributing
the Trigger for readout have been displayed before, but I think we need
the specific details listed to convince ourselves before releasing documents
to the reviewers.
3.
Cost and schedule updates
System Engineering
Hall D Drawing and Document Numbers
Description
Drawing Number
Trigger System – Top Level
D00000-16-08-0000
Level 1 Crate Trigger Processor – Fiber
Distribution
-16-08-0001
Trigger_Link and Clock Distribution – Fiber Optic
-16-08-0002
Specifications & Functional Description
FADC-250 Module
-16-08-S000
Crate Trigger Processor
-16-08-S001
Trigger Interface Module
-16-08-S002
Signal Distribution Module
-16-08-S003
Sub_System Processor Module
-16-08-S004
Global Trigger Processor Module
-16-08-S005
Trigger Supervisor Module
-16-08-S006
Trigger Distributor Module
-16-08-S007
VXS Crate Specification (JLAB Requirements)
-16-08-S010
System Engineering
Hall D Drawing and Document Numbers continued,,
Description
Drawing Number
Readout Controller Network – Top Level
D00000-16-09-0000
High Speed DAQ Subnet– Fiber Distribution
-16-09-0001
Slow Controls Subnet -- Ethernet
-16-09-0002
Terminal Server Connections
-16-09-0003
Specifications & Functional Description
Perfect place to store vendor specifications and
manuals for network gear and other commercial
equipment
-16-09-SNNN
Questions?
Discussion?
• Examples of physical rack layout drawings
• ALL equipment must be shown to identify rack space issues
(i.e. Network gear, patch panels, splitter panels, etc.)
• Airflow/Cooling issues will need to be identified and resolved
36” Deep
19” Standard JLAB Rack
VXS Crate with:
(16) FADC-250
(1)
Sum Board
(1) Clock/Trig/Sync
Cpu not shown
Fan Tray/Crate control
Latest Designs
VXS
High Speed
Serial
Backplane
z
16 channel 250 Msps Flash ADC
Energy Sum Module