Transcript Part 1 - University of Guelph

ENG3380
Computer Organization and
Architecture
“Instruction Set Architecture
(ISA) Part #1”
Winter 2017
S. Areibi
School of Engineering
University of Guelph
Topics






Introduction
Addressing Modes
Instruction Formats
MIPS Instruction Set
 Arithmetic
 Register & Memory Operands
 Immediate Operands
 MIPS R-Format Instructions
 MIPS I-Format Instructions
 Logical Operations
Compiling HLL to Assembly
 If Statements
 While Statements
 Branch Instructions
Data
With thanks to W. Stallings, Hamacher, J. Hennessy, M. J. Irwin for lecture slide contents
Many slides adapted from the PPT slides accompanying the textbook and CSE331 Course
2
References
I.
II.
III.
“Computer Organization and Architecture:
Designing for Performance”, 10th edition,
by William Stalling, Pearson.
“Computer Organization and Design: The
Hardware/Software Interface”, 4th editino, by D.
Patterson and J. Hennessy, Morgan Kaufmann
Computer Organization and Architecture:
Themes and Variations”, 2014, by Alan
Clements, CENGAGE Learning
3
Introduction
Instruction Set Design
Very complex because it affects so many aspects of the computer system
Defines many of the functions performed by the processor
Programmer’s means of controlling the processor
Fundamental design issues:
Operation repertoire
Data types
Instruction format
Registers
Addressing
•How many and which
operations to provide and
how complex operations
should be
•The various types of data
upon which operations
are performed
•Instruction length in bits,
number of addresses, size
of various fields, etc.
•Number of processor
registers that can be
referenced by instructions
and their use
•The mode or modes by
which the address of an
operand is specified
Instruction Set Architecture (ISA)
o A programmable system uses a sequence of instructions to control its
operation
or
o An typical instruction specifies: CentralProcessor
Memory
processing unit
•
•
•
•
Operation to be performed
Operands to use, and
Where to place the result, or
Which instruction to execute next
Datapath
Data
Data
and
Instructions
Registers
Instruction
register
PC
Address
register
Address
Controlpath
o Instructions are stored in RAM or ROM as a program
o The addresses for instructions in a computer are provided by a
Program Counter (PC) that can
• Count up
• Load a new address based on an instruction and, optionally, status information
Instruction Set Architecture (ISA) (continued)
 The PC and associated control logic are part of the Control Unit
 Executing an instruction - activating the necessary sequence of
operations specified by the instruction
 Execution is controlled by the control unit and performed:
• In the datapath
• In the control unit
• In external hardware such as memory or input/output
Processor or
Central processing unit
Memory
Datapath
Data
Data
and
Instructions
Registers
Instruction
register
PC
Controlpath
Address
register
Address
ISA: Storage Resources
 The storage resources are "visible" to the programmer at the lowest software
level (typically, machine or assembly language)
 Storage resources for the SC =>
 Separate instruction and
data memories imply
"Harvard architecture"
 Done to permit use of
single clock cycle per
instruction implementation
 Register File consists of
Several register for data
Manipulation.
 PC points to next instruction
to be executed.
Program counter
(PC)
Instruction
memory
215 x 16
Register file
8 x 16
Data
memory
215 x 16
Stored Program Computers
The BIG Picture
o Instructions represented in
binary, just like data
o Instructions and data stored in
memory
o Programs can operate on
programs
 e.g., compilers, linkers, …
o Binary compatibility allows
compiled programs to work on
different computers
 Standardized ISAs
Instruction Set
The vocabulary of
commands understood
by a given architecture.
o The repertoire of instructions of a computer
o Different computers have different instruction sets
 But with many aspects in common
o Early computers had very simple instruction sets
 Simplified implementation
o Many modern computers also have simple instruction
sets
Elements of a Machine Instruction
Operation code
(opcode)
Source operand
reference
• Specifies the operation
to be performed. The
operation is specified
by a binary code,
known as the operation
code, or opcode
• The operation may
involve one or more
source operands, that
is, operands that are
inputs for the
operation
Result operand
reference
Next instruction
reference
• The operation may
produce a result
• This tells the processor
where to fetch the next
instruction after the
execution of this
instruction is complete
Instruction Set Architecture

The language of the machine


Stored program (von Neumann) concept


Want an ISA that makes it easy to build the
hardware and the compiler while maximizing
performance and minimizing cost
Instructions are stored in memory (as is the data)
Our target: the MIPS ISA


similar to other ISAs developed since the 1980's
used by Broadcom, Cisco, NEC, Nintendo, Sony, …
Design goals: maximize performance, minimize
cost, reduce design time (time-to-market),
minimize memory space (embedded systems),
minimize power consumption (mobile systems)
CISC
Complex Instruction Set Computer
–
–
–
–
–
Large number of instructions
Complex Instructions (FFT, MAC, …)
Specialized Instructions
Multi-Cycle Instructions
Facilitate the extensive manipulation of low-level
computational elements and events such as
memory, binary arithmetic, and addressing.
Why CISC?
o
Since the earliest machines were programmed in assembly
language and memory was slow and expensive,
o
o
the CISC philosophy made sense, and was commonly implemented
in such large computers as the PDP-11 and the DECsystem 10 and
20 machines.
CISC was developed to make compiler development simpler.
o
It shifts most of the burden of generating machine instructions to the
processor. For example, instead of having to make a compiler write
long machine instructions to calculate a square-root, a CISC
processor would have a built-in ability to do this.
RISC
Reduced Instruction Set Computer
–
–
–
–
–
Small number of instructions
Simple type of instructions (Ld, St, Add, …)
Instruction size constant
Bans the indirect addressing mode
Retains only those instructions that can be
overlapped and made to execute in one machine
cycle or less.
CISC versus RISC
CISC
RISC
Emphasis on hardware
Emphasis on software
Includes multi-clock
complex instructions
Single-clock,
reduced instruction only
Memory-to-memory:
"LOAD" and "STORE"
incorporated in instructions
Register to register:
"LOAD" and "STORE"
are independent instructions
Small code sizes,
high cycles per second
Low cycles per second,
large code sizes
Transistors used for storing
complex instructions
Spends more transistors
on memory registers
RISC - Reduced Instruction Set Computer
 RISC
philosophy
fixed instruction lengths
 load-store instruction sets
 limited number of addressing modes
 limited number of operations

 MIPS, ARM,
Sun SPARC, HP PA-RISC, IBM
PowerPC …
 Instruction sets are measured by how well
compilers use them as opposed to how well
assembly language programmers use them
 CISC
(C for complex), e.g., Intel x86
Addressing Mode
Addressing Modes
An addressing mode refers to the process used by the
CPU to determine the location of an argument!
Immediate
Direct
Indirect
Register
Register indirect
Displacement
Stack
Operand
fetch
Instruction
fetch
Operand
store
Multiple
operands
Instruction
address
calculation
Instruction
operation
decoding
Operand
address
calculation
Instruction complete,
fetch next instruction
Multiple
results
Data
Operation
Operand
address
calculation
Return for string
or vector data
Figure 12.1 Instruction Cycle State Diagram
Source and result operands can be in one of four areas:
1) Main/Virtual memory
● As with next instruction
references, the main or virtual
memory address must be
supplied
2) I/O device
● The instruction must specify
the I/O module and device
for the operation. If
memory-mapped I/O is used,
this is just another main or
virtual memory address
3) Processor register
● A processor contains one or
more registers that may be
referenced by machine
instructions.
● If more than one register
exists each register is
assigned a unique name or
number and the instruction
must contain the number of
the desired register
4) Immediate
● The value of the operand is
contained in a field in the
instruction being executed
Addressing Modes
Instruction
Operand
Instruction
A
Instruction
A
Memory
Memory
Operand
An addressing mode
refers to the process
used by the CPU to
determine the location
of an argument!
Operand
(a) Immediate
Instruction
(b) Direct
(c) Indirect
Instruction
R
Instruction
R
A
R
Memory
Memory
Operand
Registers
(d) Register
Instruction
Implicit
Top of Stack
Register
(g) Stack
Registers
Operand
(e) Register Indirect
Registers
Operand
(f) Displacement
Addressing Modes
Each addressing mode has its advantages and disadvantages.
Mode
Algorithm
Principal Advantage
Principal Disadvantage
Immediate
Operand = A
No memory reference Limited operand magnitude
Direct
EA = A
Simple
Limited address space
Indirect
EA = (A)
Large address space
Multiple memory references
Register
EA = R
No memory reference Limited address space
Register indirect EA = (R)
Large address space
Extra memory reference
Displacement
EA = A + (R)
Flexibility
Complexity
Stack
EA = top of stack
No memory reference Limited applicability
MIPS Addressing Modes
An addressing mode
refers to the process
used by the CPU to
determine the location
of an argument!
Instruction Formats
Instruction Formats
Define the
layout of the
bits of an
instruction, in
terms of its
constituent
fields
Must include
an opcode and,
implicitly or
explicitly,
indicate the
addressing
mode for each
operand
For most
instruction sets
more than one
instruction
format is used
4 bits
6 bits
6 bits
Opcode
Operand Reference
Operand Reference
Instruction Representation
o Within the computer each instruction is represented by a
sequence of bits
o The instruction is divided into fields, corresponding to the
constituent elements of the instruction
4 bits
6 bits
6 bits
Opcode
Operand Reference
Operand Reference
16 bits
Figure 10.2 A Simple Instruction Format
Figure 12.2 A Simple Instruction Format
Instruction Representation
o Operation Codes (Opcodes) are represented
by abbreviations called mnemonics
o Examples include:
 ADD
 Add
 SUB
 Subtract
 MUL
 Multiply
 DIV
 Divide
 LOAD
 Load data from memory
 STOR
 Store data to memory
o Operands are also represented symbolically
o Each symbolic opcode has a fixed binary representation
 The programmer specifies the location of each symbolic operand
Instruction Types
•Arithmetic instructions provide
•Movement of data into or
computational capabilities for processing
numeric data
•Logic (Boolean) instructions operate on
the bits of a word as bits rather than as
numbers, thus they provide capabilities
for processing any other type of data the
user may wish to employ
•Test instructions are used to test the
value of a data word or the status of a
computation
•Branch instructions are used to
branch to a different set of instructions
depending on the decision made
out of register and or
memory locations
Data
processing
Data
storage
Control
Data
movement
•I/O instructions are
needed to transfer programs
and data into memory and
the results of computations
back out to the user
Instruction
SUB Y, A, B
MPY T, D, E
ADD T, T, C
DIV
Y, Y, T
Comment
Y¬A–B
T¬D´E
T¬T+C
Y¬Y÷T
Instruction
Comment
LOAD
MPY
ADD
STOR
LOAD
SUB
DIV
STOR
AC ¬ D
AC ¬ AC ´ E
AC ¬ AC + C
Y ¬ AC
AC ¬ A
AC ¬ AC – B
AC ¬ AC ÷ Y
Y ¬ AC
(a) Three-address instructions
Instruction
MOVE Y, A
SUB Y, B
MOVE T, D
MPY T, E
ADD T, C
DIV
Y, T
Comment
Y¬A
Y¬Y–B
T¬D
T¬T´E
T¬T+C
Y¬Y÷T
(b) Two-address instructions
Programs to Execute Y =
D
E
C
Y
A
B
Y
Y
(c) One-address instructions
A-B
C + (D ´ E)
Figure 12.3 Programs to Execute Y=
A- B
C+ (D´ E)
Operands
Types of Operands
Numbers
o All machine languages include numeric data types
o Numbers stored in a computer are limited:
● Limit to the magnitude of numbers representable on a machine
● In the case of floating-point numbers, a limit to their precision
o Three types of numerical data are common in computers:
● Binary integer or binary fixed point
● Binary floating point
● Decimal
o Packed decimal
● Each decimal digit is represented by a 4-bit code with two digits stored per byte
● To form numbers 4-bit codes are strung together, usually in multiples of 8 bits
Byte unsigned integer
7
0
Word unsigned integer
15
0
Doubleword unsigned integer
31
0
Quadword unsigned integer
63
0
sign bit
twos comp
7
0
sign bit
15
0
sign bit
31
0
sign bit
63
0
sign bit
signif.
exp
15
9
0
sign bit
exp
31
significand
22
0
sign bit
exp
63
sign bit
51
0
Word signed integer
(twos complement)
Doubleword signed integer
(twos complement)
Quadward usigned integer
(twos complement)t
Half precision
floating point
Single precision
floating point
Double precision
floating point
integer bit
exponent
79
significand
Byte signed integer
(twos complement)
significand
63
0
Double extended precision
floating point
Figure 12.4 x86 Numeric Data Formats
Byte unsigned integer
7
0
Word unsigned integer
15
0
Doubleword unsigned integer
31
0
Quadword unsigned integer
63
0
sign bit
twos comp
7
0
sign bit
15
0
sign bit
31
0
sign bit
63
0
sign bit
signif.
exp
15
9
0
sign bit
exp
31
significand
22
0
sign bit
exp
63
sign bit
51
0
Word signed integer
(twos complement)
Doubleword signed integer
(twos complement)
Quadward usigned integer
(twos complement)t
Half precision
floating point
Single precision
floating point
Double precision
floating point
integer bit
exponent
79
significand
Byte signed integer
(twos complement)
significand
63
0
Double extended precision
floating point
Figure 12.4 x86 Numeric Data Formats
Byte unsigned integer
7
0
Word unsigned integer
15
0
Doubleword unsigned integer
31
0
Quadword unsigned integer
63
0
sign bit
twos comp
7
0
sign bit
15
0
sign bit
31
0
sign bit
63
0
sign bit
signif.
exp
15
9
0
sign bit
exp
31
significand
22
0
sign bit
exp
63
sign bit
51
0
Word signed integer
(twos complement)
Doubleword signed integer
(twos complement)
Quadward usigned integer
(twos complement)t
Half precision
floating point
Single precision
floating point
Double precision
floating point
integer bit
exponent
79
significand
Byte signed integer
(twos complement)
significand
63
0
Double extended precision
floating point
Figure 12.4 x86 Numeric Data Formats
Byte unsigned integer
7
0
Word unsigned integer
15
0
Doubleword unsigned integer
31
0
Quadword unsigned integer
63
0
sign bit
twos comp
7
0
sign bit
15
0
sign bit
31
0
sign bit
63
0
sign bit
signif.
exp
15
9
0
sign bit
exp
31
significand
22
0
sign bit
exp
63
sign bit
51
0
Word signed integer
(twos complement)
Doubleword signed integer
(twos complement)
Quadward usigned integer
(twos complement)t
Half precision
floating point
Single precision
floating point
Double precision
floating point
integer bit
exponent
79
significand
Byte signed integer
(twos complement)
significand
63
0
Double extended precision
floating point
Figure 12.4 x86 Numeric Data Formats
ASCI Characters
o A common form of data is text or character strings
o Textual data in character form cannot be easily stored or
transmitted by data processing and communications
systems because they are designed for binary data
o Most commonly used character code is the International
Reference Alphabet (IRA)
 Referred to in the United States as the American Standard
Code for Information Interchange (ASCII)
o Another code used to encode characters is the Extended
Binary Coded Decimal Interchange Code (EBCDIC)
 EBCDIC is used on IBM mainframes
Logical Data
o An n-bit unit consisting of n 1-bit items of data, each item
having the value 0 or 1
o Two advantages to bit-oriented view:
 Memory can be used most efficiently for storing an array of
Boolean or binary data items in which each item can take on
only the values 1 (true) and 0 (false)
 To manipulate the bits of a data item
♦ If floating-point operations are implemented in software, we
need to be able to shift significant bits in some operations
♦ To convert from IRA to packed decimal, we need to extract the
rightmost 4 bits of each byte
Byte Ordering and Endianness
 Processors can order bytes within a word in two ways
 Little Endian Byte Ordering
 Memory address = Address of least significant byte
 Example: Intel IA-32, Alpha
MSB
LSB
Byte 3 Byte 2 Byte 1 Byte 0
32-bit Register
a+1
a+2
a+3
address a
. . . Byte 0 Byte 1 Byte 2 Byte 3
...
Memory
 Big Endian Byte Ordering
 Memory address = Address of most significant byte
 Example: SPARC, PA-RISC
MSB
LSB
Byte 3 Byte 2 Byte 1 Byte 0
32-bit Register
a+1
a+2
a+3
address a
. . . Byte 3 Byte 2 Byte 1 Byte 0 . . .
Memory
MIPS Instruction Set
The MIPS Instruction Set
o Used as the example throughout the course (book)
o Stanford MIPS commercialized by MIPS Technologies
• www.mips.com
• https://imgtec.com/mips
o Large share of embedded core market
 Applications in consumer electronics, network/storage equipment,
cameras, printers, …
o Typical of many modern ISAs
 ARM, …
Similarities in ARM and MIPS instruction sets.
Overview of the MIPS ISA
Registers
 All instructions are 32-bit wide
R0 - R31
PC
HI
 Three Instruction Formats
LO
R-type
Op6
Rs5
Rt5
I-type
Op6
Rs5
Rt5
J-type
Op6
Rd5
sa5
immediate16
immediate26
funct6
o
All instructions are 32-bit wide
o
Instruction Categories:
R-type:
31
25
op
I-Type:
31
20
rs
25
op
R-type:
31
I-Type:
31
op
rt
20
rs
25
op
15
rs
25
rs
rd
10
5
shamt funct
15
rt
rt
20
rt
0
address offset
15
20
0
rd
10
5
0
shamt funct
15
0
address offset
J-Type:
31
op
0
jump target address
Arithmetic Operations
o Add and subtract, three operands
 Two sources and one destination
add a, b, c
# a gets b + c
o All arithmetic operations have this form
o Design Principle 1: Simplicity favors regularity
 Regularity makes implementation simpler
 Simplicity enables higher performance at lower cost
R-type
Op6
Rs5
Rt5
Rd5
sa5
funct6
A Basic MIPS Instruction
C code:
a=b+c;
Assembly code: (human-friendly machine instructions)
add a, b, c
# a is the sum of b and c
Machine code: (hardware-friendly machine instructions)
00000010001100100100000000100000
Translate the following C code into assembly code:
a = b + c + d + e;
47
Example
C code a = b + c + d + e;
translates into the following assembly code:
add a, b, c
add a, a, d
add a, a, e
or
add a, b, c
add f, d, e
add a, a, f
• Instructions are simple: fixed number of operands (unlike C)
• A single line of C code is converted into multiple lines of
assembly code
• Some sequences are better than others…
– the second sequence needs one more (temporary) variable f
48
Arithmetic Example
o C code:
f = (g + h) - (i + j);
o Equivalent Assembly Code:
add t0, g, h
add t1, i, j
sub f, t0, t1
# temp t0 = g + h
# temp t1 = i + j
# f = t0 - t1
Register Operands
o Arithmetic instructions use register operands
o MIPS has a 32 × 32-bit register file
 Use for frequently accessed data
 Numbered 0 to 31
 32-bit data called a “word”
o Assembler names
 $t0, $t1, …, $t9 for temporary values
 $s0, $s1, …, $s7 for saved variables
o Design Principle 2: Smaller is faster
 c.f. main memory: millions of locations
MIPS Register File
 Operands
of arithmetic instructions must be from a
limited number of special locations contained in the
Register File
datapath’s register file

Thirty-two 32-bit registers
- Two read ports
- One write port
 Registers

are
Fast
src1 addr
src2 addr
dst addr
write data
5
5
5
32 src1
data
25 =32
locations
32 src2
32
data
32 bits
- Smaller is faster & Make the common case fast

Easy for a compiler to use
- e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order

Improves code density
- Since register are named with fewer bits than a memory location
 Register
addresses are indicated by using $
Naming Conventions for Registers
0
$zero constant 0 (Hdware)
16 $s0 callee saves
1
$at reserved for assembler
...
2
$v0 expression evaluation &
23 $s7
3
$v1 function results
24 $t8 temporary (cont’d)
4
$a0 arguments
25 $t9
5
$a1
26 $k0 reserved for OS kernel
6
$a2
27 $k1
7
$a3
28 $gp pointer to global area
8
$t0 temporary: caller saves
29 $sp stack pointer
(callee can clobber)
30 $fp frame pointer
...
15 $t7
(caller can clobber)
31 $ra return address (Hdware)
Register Operand Example
o C code (Same Example Again):
f = (g + h) - (i + j);
 f, …, j in $s0, …, $s4
o Compiled MIPS code:
add $t0, $s1, $s2
add $t1, $s3, $s4
sub $s0, $t0, $t1
Processor – Memory Interconnections
 Memory
is a large, single-dimensional array
 An address acts as the index into the memory
array
The word
address of the
data
Memory
read addr/32
write addr
Processor
?
locations
read data32
32write data
The data stored
in the memory
10
101
1
8
4
0
232 Bytes
(4 GB)
 230 Words
(1 GW)
32 bits = 4 Bytes = 1 Word
Memory Operands
o Main memory used for composite data
● Arrays, structures, dynamic data
o To apply arithmetic operations
● Load values from memory into registers (lw)
● Store result from register to memory (sw)
o Memory is byte addressed
● Each address identifies an 8-bit byte
o Words are aligned in memory
● Address must be a multiple of 4 (Important)
o MIPS is Big Endian
● Most-significant byte at least address of a word
● c.f. Little Endian: least-significant byte at least address
Accessing Memory
I-Type:
31
op
25
rs
20
15
rt
0
address offset
 MIPS
has two basic data transfer instructions for
accessing memory (assume $s3 holds 2410)
lw
sw
 The
$t0, 4($s3) #load word from memory
28
$t0, 8($s3) #store word to memory
32
data transfer instruction must specify
where in memory to read from (load) or write to (store)
– memory address
 where in the register file to write to (load) or read from
(store) – register destination (source)

 The
memory address is formed by summing the
constant portion of the instruction and the
contents of the second register
MIPS Memory Addressing
 The
memory address is formed by summing the
constant portion of the instruction and the
contents of the second (base) register
$s3 holds 8
Memory
. . . 0001
lw
sw
$t0, 4($s3)
$t0, 8($s3)
...0110
24
...0101
20
...1100
16
...0001
12
...0010
8
...1000
4
...0100
32 bit Data
0
Word Address
. . . 0001
#what? is loaded into $t0
#$t0 is stored where?
in location 16
Compiling with Loads and Stores
variable b is stored in $s2 and that
the base address of array A is in $s3, what is
the MIPS assembly code for the C statement
A[8] = A[2] - b
 Assuming
...
...
A[3]
$s3+12
A[2]
$s3+8
A[1]
$s3+4
A[0]
$s3
I-type
Op6
Rs5
lw
$t0, 8($s3)
sub
$t0, $t0, $s2
sw
$t0, 32($s3)
Rt5
immediate16
Memory Operand Example 1
o C code:
g = h + A[8];
 g in $s1, h in $s2, base address of A in $s3
o Compiled MIPS code:
 Index 8 requires offset of 32
♦ 4 bytes per word (so offset  4x8=32)
lw $t0, 32($s3)
add $s1, $s2, $t0
offset
# load word
# g = h + A[8]
base register
Memory Operand Example 2
o C code:
A[12] = h + A[8];
 h in $s2, base address of A in $s3
o Compiled MIPS code:
 Index 8 requires offset of 32
 Index 12 requires offset of 48
lw $t0, 32($s3)
add $t0, $s2, $t0
sw $t0, 48($s3)
# load word
# Add
# store word
Registers vs. Memory
o Registers are faster to access than memory
o Operating on memory data requires loads and stores
 More instructions to be executed
o Accessing registers also uses less energy than accessing
memory.
o Compiler must use registers for variables as much as
possible
 Only spill to memory for less frequently used variables
 Register optimization is important!
Dealing with Constants

Small constants are used quite frequently (50%
of operands in many common programs)
e.g.,

A = A + 5;
B = B + 1;
C = C - 18;
Solutions? Why not?



Put “typical constants” in memory and load them
Create hard-wired registers (like $zero) for
constants like 1, 2, 4, 10, …
How do we make this work?

How do we Make the common case fast !
Constant (or Immediate) Operands

Include constants inside arithmetic instructions


Much faster than if they have to be loaded from memory
(they come in from memory with the instruction itself)
MIPS immediate instructions
addi $s3, $s3, 4
I-type
Op6
Rs5
Rt5
#$s3 = $s3 + 4
immediate16
There is no subi instruction, can you guess why
not?
Immediate Operands
o Constant data specified in an instruction
addi $s3, $s3, 4
o No subtract immediate instruction
 Just use a negative constant
addi $s2, $s1, -1
o Design Principle 3: Make the common case fast
 Small constants are common
 Immediate operand avoids a load instruction
The Constant Zero
o MIPS register 0 ($zero) is the constant 0
 Cannot be overwritten
o Useful for common operations
 E.g., move between registers
add $t2, $s1, $zero
MIPS Instruction Format
R-type:
31
op
• The two MIPS instruction formats so far are R and I.
• The first16 bits are the same:
25
rs
20
rt
15
rd
10
5
0
shamt funct
I-Type:
31
25
20
15
rs
op
rt address offset
• both contain an op field, giving the base operation;
• an rs field, giving one of the sources;
• and the rt field, which specifies the other source operand, except for load word, where it
specifies the destination register.
• R-format divides the last 16 bits into:
• an rd field, specifying the destination register;
• the shamt field, (explained later);
• and the funct field, which specifies the specific operation of R-format instructions.
• I-format combines the last 16 bits into a single address field.
0
MIPS Instructions, so far ..
Category
Instr
Arithmetic add
Data
transfer
Example
Meaning
add $s1, $s2, $s3 $s1 = $s2 + $s3
subtract
sub $s1, $s2, $s3 $s1 = $s2 - $s3
add
immediate
addi $s1, $s2, 4
$s1 = $s2 + 4
load word
lw
$s1, 32($s2)
$s1 = Memory($s2+32)
store word
sw $s1, 32($s2)
Memory($s2+32) = $s1
Review: MIPS Organization
 Arithmetic
instructions – to/from the register file
 Load/store
instructions - to/from memory
Memory
Processor
src1 addr
src2 addr
Register
File
5
1…1100
src1
data
32
32
5
registers
dst addr ($zero - $ra)
src2
5
write
32 data
data 32
32 bits
32 ALU
32
read/write
addr
230
word
s
32
read data
32
write data
32
32
4
0
byte address
(big Endian)
5
1
6
2
32 bits
7
3
0…1100
0…1000
0…0100
0…0000
word address
(binary)
Summary
Computer Architecture includes the design of the
Instruction Set Architecture (programmer’s view)
and the Machine Organization (logic designer’s
view).
Instruction Set Design is a complex process since it
affects many aspects of the computer system.
Fundamental Design Issues (decisions):
I.
II.
III.
I.
II.
III.
IV.
V.
How many and which operations to provide …
Defining the data types upon which operations will be
performed.
Instruction length in bits, number of addresses, size of
various fields,
Number of processor registers that can be referenced by
instructions and their use
The mode or modes by which the address of an operand is
specified
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