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ES C263 Microprocessor
Programming and Interfacing
BITS Pilani
Pilani Campus
Pawan Sharma
08-01-2013
Last Lecture
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Course Overview
Microprocessor based systems
Evolution of microprocessors
Moore’s law
BITS Pilani, Pilani Campus
Today’s Lecture
 Instruction Set Architecture
 Design Example
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The Personal Computer
Speaker
Timer logic
(8253)
Processor (8086
through Pentium
Coprocessor (8087
trough 80387
System ROM
640KB
DRAM
System bus (data, address & control signals)
Keyboard logic (8255)
Keyboard
DMA Controller (8237)
Expansion logic
Interrupt logic (8259)
Disk controller
Video card
Serial port
...
Extension slots
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Clock
 A clock signal is a particular type of signal that oscillates
between a high and a low state and is utilized like
a metronome (device that produces regular, metrical ticks
(beats, clicks) to coordinate actions of circuits.
 The clock rate or frequency of a CPU is determined by
the frequency of the clock signal generated from an oscillator
crystal.
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Instruction Set Architecture (ISA)
An instruction set architecture is the part of the computer
architecture related to programming, including the native data
types, instructions, registers, addressing modes, memory
architecture, interrupt and execution and exception handling
and external I/O.
ISA refers to the actual set of programmer visible instruction
set.
Serves as a boundary between the hardware and software.
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Seven dimensions of ISA
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Class of ISA: nearly all ISAs are general purpose register architectures,
where operands are either memory or register locations.
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Register memory (8086): can access memory as part of many instructions
Load-store(ARM, MIPS): can access memory with only load and store instructions
• Memory Addressing: Byte addressing to access memory locations—
aligned or un-aligned.
• Addressing Modes: specify the address of register, constant operands and
memory objects-- register, immediate, displacement.
• Types and sizes of operands: supports operand sizes of 8 bit, 16 bit, 32 bit.
• Operations: data transfer, arithmetic, logic, control.
• Control flow instructions: support conditional branches, unconditional
jumps, procedure calls and returns.
• Encoding an ISA: fixed length or variable length.
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
Microprocessor
-Fetches Instruction
-Executes Instruction
BITS Pilani, Pilani Campus
Computer Hardware Organization
Control
unit
common bus
Arithmetic
logic
unit
memory
Registers
program
storage
data
storage
output
input
unit
unit
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Add
Bus
CPU
Data
Bus
Control
signals
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Add Bus
Data Bus
Memory
Read
Write
Memory – Registers to hold bits
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Ex :
4 bits
Add lines : 3 (Unidirectional)
8 Registers
Data lines : 4 (Bidirectional)
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
RAM
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Design Example
BITS Pilani, Pilani Campus
Design a microprocessor based system to control
pH of a solution in a reactor tank.
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User enters desired pH
(0-14) and controller
gain
Reactor
tank
is
provided with three pH
sensors, to compute
the average pH.
Motorised
valve
Reactor tank has three
inputs.
• (acid flow, base flow
effluent discharged
from factory
controlled by valves)
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Valve Control
-Controlled by stepper motors
-1 step is by 1.8 degrees rotation
Valve opening = kP * error
Where error = desired pH – measured pH.
Error positive- close fully acid valve and open base valve accordingly
Error negative- close fully base valve and open acid valve accordingly.
0 – 360 degrees correspond to 0 to 200 steps.
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Stepper Motor sequence:
A B
1
0
0
1
1
0
1
1
0
0
C D
1
1
0
0
1
0
0
1
1
0
CW
ACW
Use a 4- bit port + driver (nearly 1 A current)
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pH sensor
Vout
0
7
14
pH
Voltage output 60mV/pH
-420mV - +420mV
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Interfacing Analog to Digital
Converter
8-bit ADC
I0
D0
I7
D7
Start
A
B
C
ALE
EOC
OE
ADC 0809
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Input Keys
- Numeric keys 0 – 9
- Function keys
pH, kP, enter
Matrix Keypad interfacing!!
- 2 four bit ports.
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Display Device and storage
Two digit Display
 Two seven segment display devices to
display pH
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Memory Interfacing
 ROM
(4KB) - FF000H – FFFFFH
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- SRAM (4K) - 00000H – 00FFFH
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System Block Diagram
Parallel
I/O
CPU
Memory
Serial
I/O
I/O Interface
Data
Address
Control
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Method of Approach
Identify input and output devices
Memory requirements
Suitable memory and I/O interfacing
Assembly Language Programming
Assumptions made
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BITS Pilani, Pilani Campus