Transcript Microarchitecture Overview: Microinstructions Control – The Mic-1

CE 454
Computer Architecture
Lecture 7
Ahmed Ezzat
The Microarchitecture Level,
Ch-4.1, 4.2, 4.3
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Outline
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Microarchitecture Overview
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IJVM
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Stacks
Memory Model
Instruction Set
Compiling Java to IJVM
Example
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Data Path
Microinstructions
Microinstruction Control: The Mic-1
Microinstructions and Notation
Implementation of IJVM Using the Mic-1
Reading Assignment: Simulation documentation
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Microarchitecture Overview
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Microarchitecture is the next-level up above the digital logic. It
implements the ISA (Instruction Set Architecture), which is the level
above it
Our chosen ISA is a subset of JVM – only Integer instructions and
hence IJVM
This level is a micro-program that will execute IJVM instructions
Micro-program has simple instructions and state (values assigned to
variables)
State changes as code executes
Machine runs in a fetch-execute loop
– Fetches instruction (opcode =operation code)
– Fetches operands (data)
– Executes
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Microarchitecture Overview: Data Path
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Part of the CPU
containing ALU, its
inputs and outputs
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Some registers
have symbolic
names MAR, MDR,
PC, etc.
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Microarchitecture Overview: Data Path
Notations
 These registers are
accessible only at the
microarchitecture level
 Registers can write data into
gray B bus
 C bus writes data into
registers
 Light arrows exchange data
with memory
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Microarchitecture Overview: Data Path
Operations
 Operands to ALU come from
register H and bus B
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Note: H is written as output
from Shifter – output from
previous ALU operation
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Six control lines for ALU, one
for Shift control
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Microarchitecture Overview: Data Path
Control Signals to ALU
 Not all of these are needed
for our IJVM
 ENA, ENB –enable A, B
 INVA –invert A,
 INC – increase by 1
 Can load ALU, pass the
data through Shifter and
store it in H in the same
cycle.
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Microarchitecture Overview: Data Path
Data Path Timing
 Have four sub-cycles
(implicit) in a clock cycle
– Control signal setup (Δw)
– Load register into B-bus
(Δx)
– ALU & shifter op (Δy)
– Result back to registers
along C bus (Δz)
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Microarchitecture Overview: Data Path
Data Path Timing
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Starts with falling edge
of clock
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Ends with rising edge
of clock
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(Clock cycle) > (Δw +
Δx + Δy + Δz)
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Microarchitecture Overview: Data Path
Memory Operations
 Have 32 bit wordaddressable port and 8
bit byte addressable
port (controlled by PC)
 MAR, MBR, PC are
registers
 MBR can only output
data to bus B in two
formats
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Microarchitecture Overview: Data Path
Memory Operations
 MBR, MAR, PC driven by control signals
 MAR, H does not have enable signals -always on
 MAR has word addresses, PC has byte addresses
 Resulting memory fetch will be put into low order 8 bits of MBR
 PC/MBR is used to read instructions (executable byte stream).
All,other registers use words
 MAR/MDR used to read operands (word boundary)
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PC = 2 memory reads, out byte-2
MAR = 2 memory reads, out bytes 8-11(word-2 which is 4 bytes)
Output of MBR gated to bus B
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Microarchitecture Overview: Data Path
Output Formats of MDR
 8-bit Unsigned Values:
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Signed value between –127 and +127:
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Used for indexes or part of 16 bit integers
Put into low 8 bits in bus B
Zeros in upper 24 bits
Copy MBR sign bit (leftmost 8) into 24 leftmost bits
Put numerical value into 8 rightmost bits
(known as sign extension)
That is why there are two lines from MBR to B
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Microarchitecture Overview: Data Path
Need 29 Signals
 9 to write from C bus into
registers
 9 to write to B bus for ALU input
 8 to control ALU and shifters
functions
 2 to indicate r/w to MAR/MDR
 1 for memory fetch via PC/MBR
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Microarchitecture Overview:
Microinstructions
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Cycle =
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Gating values on to B
Propagating values through ALU and shifters
Driving signals on to C bus
Writing results in registers
If memory r/w asserted, initiate action
Memory operation started at end of cycle
Data available only after next cycle. (one cycle missed!)
May write value in C onto more than one register, but never put
value onto B from more than one register
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Microarchitecture Overview:
Microinstructions
Microinstructions Formats
 To select inputs to B bus need 4-bits (2**4=16), only 9 are needed
 Bits needed for controlling data path = 9+4+8+2+1 = 24-bits for
one cycle
 NEXT_ADDRESS and JAM needed to indicate next instruction to
be fetched
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Microarchitecture Overview:
Microinstructions
Microinstructions Formats
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Addr: potential next
address
JAM how next
microinstruction is
selected
C: Which register
written from C
Mem: memory
function
B: Source of B
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Microarchitecture Overview:
Microinstructions Control – The Mic-1
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Sequencer steps through operations to execute each ISA
instruction providing. Produces every cycle the following:
– State of each control signal (asserted or not)
– Address of next instruction
Control Store = holds microprogram, made of read only memory
(logic gates)
Example control store contain 512, 36 bit words
Each microinstruction specifies its successor
Needs own
– counter = MPC (Microprogram counter)
– Memory data register = MIR (Microinstruction register)
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Microarchitecture Overview:
Microinstructions Control: The Mic-1
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Microarchitecture Overview:
Microinstructions Control: The Mic-1
MPC, MIR
 “B” 4-bits drives 4 to16 decoder
to determine what goes on B
bus
 Steps (sub-cycles):
– At falling edge MIR loaded
from word in control store
pointed by MPC (s-Cycle 1)
– Signals propagate to data
paths and register put onto
bus B
– ALU knows operation (sCycle 2)
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Microarchitecture Overview:
Microinstructions Control: The Mic-1
MPC, MIR
 Steps (Contd.):
– ALU, N, Z stable output in
s-Cycle 3
– Output propagates to
register via C bus
– Registers, N, Z loaded in
s-Cycle 4
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Microarchitecture Overview:
Microinstructions Control: The Mic-1
Determining Next Microinstruction
 Starts when MIR is stable
 NEXT-ADDRESS copied to MPC
– If JAM is 000 nothing more is done
 Else
– If JAMN is set, N-bit is ORed to higher order bit of MPC
– If JAMZ is set, Z-bit is ORed to higher order bit of MPC
 Why?
– Because after rising edge of clock bus B outputs are no longer
valid: ALU outputs not reliable, hence save status in N and Z
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Microarchitecture Overview:
Microinstructions Control: The Mic-1
Determining Next Microinstruction
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High Bit set
Boolean Function computed in
Logic Gate =
– (JAMZ and Z) or
– (JAMN and N) or
– NEXT_ADDRESS[8]
MPC takes either of:
– NEXT_ADDRESS
– NEST_ADDRESS with higher
order bit Ored with 1
If high-order bit of NEXT_ADDRESS
is 1, JAMN and JAMZ are not
relevant
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Microarchitecture Overview:
Microinstructions Control: The Mic-1
Determining Next Instruction: Example
 Current Instruction @ 0x75 has NEXT_ADDRESS = 0X92.
– If Z bit is 0, next instruction = 0x92, else 0x192
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Microarchitecture Overview:
Microinstructions Control: The Mic-1
Using MBR for Next Address Computation
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If JMPC set, 8 MBR bits bitwise Ored with 8 low order bits of NEXT_ADDRESS field
When JMPC is 1, 8 low order bits of NEXT_ADDRESS is zero, higher order is 0 or 1
So NEXT_ADDRESS becomes 0x000 or 0x100
If JMPC is zero, passes NEXT_ADDRESS to MPC as is
Allows multi-way branching (jump), MBR has opcode
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Microarchitecture Overview:
Microinstructions Control: The Mic-1
How Microinstructions Work: Summary
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SubCycle 1: MIR loaded from address in MPC
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SubCycle 2: MIR propagated out, B loaded
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SubCycle 3: ALU, Shifter produce stable value
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SubCycle 4: C, Memory and ALU stable
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Registers loaded from C
N, Z loaded
MBR, MDR get values from memory (If started in previous cycle)
MPC gets value
New cycle begins
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An Example ISA: IJVM
Stacks
IJVM: Integer Java Virtual Machine
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Stacks: Used to implement
procedures
Stack frames are used to
store:
– Local variables
(environment)
– Temporary results of
arithmetic computations
LV bottom, SP top of stack.
– Base+offset addressing
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An Example ISA: IJVM
Stacks
Operand Stacks for Arithmetic
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Stacks are rarely used for arithmetic operations
Could be mixed in with local variable stack
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An Example ISA: IJVM
The IJVM Memory Model
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Memory = 4GB = 1 GB array of 4 byte words
Unlike most ISA, JVM does not make addresses visible at the ISA level.
Instead ISA instruction index based on a base address.
4 Separate areas of memory are defined:
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Constant Pools (CPP):
 Contain constants, strings, and pointers to other areas
 Cannot be written by an IJVM program.
 Loaded when program is bought into memory
 CPP is an implicit register that points to the beginning address
Local Variables (LV):
 For each method (function, procedure) there is a frame (local variable
frame)
 Beginning has (in and out) parameters
 LV is the beginning of Local Variable stack
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An Example ISA: IJVM
The IJVM Memory Model
Contd.
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Operand Stack (SP)
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Method Area
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Text area of code reside here – treated as byte array
PC points to an address containing the next instruction to be fetched.
All addresses (CPP, LV, SP) refer to words (4 byte), except PC refers to
bytes
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Not to exceed a certain size, computed at Java compile time
Directly above LV stack.
SP indicate top/end of the stack
E.g.: LV+4 refers to 4th word after LV.
E.g.: PC +1 refer to next byte after PC
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An Example ISA: IJVM
The IJVM Memory Model
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An Example ISA: IJVM
The IJVM Instruction Set
IJVM Assembly Instructions (Macroarchitecture)
 Instructions consists of an opcode and optional operands,
encoded in Hex
 Instructions work as:
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Push words onto stack from various sources
 Constant pool: LDC_W
 Local variable frame: ILOAD
 Instruction set: BIPUSH
Compute
Pop words and store in local variable frame ISTORE
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An Example ISA: IJVM
The IJVM Instruction Set
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An Example ISA: IJVM
The IJVM Instruction Set
IJVM Assembly Instructions
 Some instructions come in various forms, IJVM will support:
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Two Arithmetic operations:
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IAND, IOR
4 Branch Operations: offset follows opcode
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IADD, ISUB
Two Logical Operations:
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Long general format
Frequently used short format
GOTO, IFEQ, IFLT, IF_ICMPEQ
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An Example ISA: IJVM
The IJVM Instruction Set
Call and Return Instructions
 INVOKEVIRTUAL
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IRETURN
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Invokes another method
Caller pushes callee address onto stack OBJREF
Caller pushes in parameters onto stack
INVOKEVIRTUAL is executed
IJVM limitation: method can invoke a method existing within its own
object, i.e., address of called procedure is determined by the CALL
instruction
Returns to caller or return from callee
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An Example ISA: IJVM
The IJVM Instruction Set
IJNVOKEVIRTUAL
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An Example ISA: IJVM
The IJVM Instruction Set
Format of Method
 Disp in INVOKEVIRTUAL points to constant pool location that
has the method address
 First word (4 bytes) in method has special data
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First two bytes
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Have # of parameters, with OBJREF counted as parameter 0
LV points to OBJREF (parameter 0)
Size of local variable area of the method being invoked
Needed to allocate stack for new call
Finally 5th byte has first opcode to be executed
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An Example ISA: IJVM
The IJVM Instruction Set
INVOKEVIRTUAL Execution
 Compute # of parameters (I.e., parameter 0 is the OBJREF) using
the first 2-bytes in the method area
 Compute base address of new stack using the second 2-bytes
(procedure local variable size) in the method area
 Set LV to OBJREF. Then erase value there and put address at
end of stack (increase by size of stack)
 At this location put old PC, next put Callers LV, and reset SP to
this address (I.e., callers LV is top-of-stack)
 Set PC to 5th byte in method code, i.e., opcode to first instruction
to be executed
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An Example ISA: IJVM
The IJVM Instruction Set
IRETURN
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An Example ISA: IJVM
The IJVM Instruction Set
Executing IRETURN
 Reverse INVOKEVIRTUAL instruction
 De allocate space for this stack frame
 Return value is placed at top of stack
 Use link pointer to restore PC and LV of the callee respectively
 SP is set to point to the return value location
 In the next cycle, go back to instruction after the call in callee.
 No explicit I/O in IJVM, they are done by special methods which
perform the I/O
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An Example ISA: IJVM
Compiling Java to IJVM
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An Example ISA: IJVM
Compiling Java to IJVM
Operand Stack
 Local variables are (i, j, k) in that order
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Horizontal line: empty stack
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An Example IJVM Implementation:
Microinstructions and Notations
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Use Higher level syntax (MAL – Micro Assembly Language) to indicate
micro-program operations, i.e., instead of describing the control store in
binary (36-bits per word). MAL reflects the microarchitecture
Each instruction can be executed in one cycle (4 sub-cycles)
During one cycle: any register can be written (typically one). Only one
register can be gated to the B bus
The A bus side of the ALU can have only +1, 0, -1, Register H
Example: MDR = H + SP
– Load SP to B
– Load H and B to ALU and add them
– Store the result back in MDR
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An Example IJVM Implementation:
Microinstructions and Notations
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Be Careful: MDR = SP + MDR is not legal as it needs more than one cycle
So is H = H - MDR as subtrahend must be in H
We extend our notations to include multiple equal signs
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Memory read write indicated by rd, wr, WSP
Reads and writes happen in 4 byte words through 4-byte words using
MAR/MDR, and indicated using rd and wr
Reads and writes of 1 byte using PC/MBR, and indicated using fetch as the
opcode
Both kinds of memory operations can proceed concurrently
One register can’t received data from memory and data path in same cycle
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SP = MDR = SP + 1
MAR = SP; rd //set MAR to SP and initiate rd operation into MDR
MDR = H
// set MDR to H
At the second cycle we have conflict!
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An Example IJVM Implementation:
Microinstructions and Notations
Legal Instructions
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An Example IJVM Implementation:
Microinstructions and Notations
Microinstructions: Addressing
 Each instruction explicitly supplies the next instruction’s address
 Explicit jumps given by goto Label
 Data path is available during a goto instruction; typically every line should
have goto, except when target is the next line, it may be omitted
 Additional notations for branches:
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Extend MAL to support 2 New registers N, Z
Z = TOS
// runs TOS through ALU and set the Z & N flip-flops
Notation for setting the JAMZ bit is
– If (Z) goto L1; else goto L2
– Z = TOS; if (Z) goto L1; else goto L2
– Hardware requires that L1 and L2 have same low-order 8-bits
(NEXT_ADDRESS is 9-bits), i.e., L1 = L2 + 256
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An Example IJVM Implementation:
Microinstructions and Notations
Microinstructions: Addressing
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Notation to set JMPC bit
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Goto (MBR OR Value)
Use value for NEXT_ADDRESS and set JMPC bit to enable ORing MBR
(low-order 8-bits) with NEXT_ADDRESS into MPC.
If value = 0, it is sufficient to write
 Goto (MBR)
Figure 4-17 gives the micro code with 112 instructions
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An Example IJVM Implementation:
Microinstructions and Notations
Part of Fig 4-17
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Example: IJVM
implementation
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An Example IJVM Implementation:
Implementation of IJVM Using the Mic-1
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112 microinstructions (microprogram) that runs on Mic-1 to interpret IJVM
assembly instructions
Additional Registers
– TOS: cache for memory location pointed to by the SP
– OPC: temporary scratch register
Has main loop (main1:) to run the
– fetch-decode-execute cycles for IJVM instructions
At the beginning of each IJVM instruction
– PC is incremented (pointing to the byte after the opcode). Current
opcode is already fetched into MBR
– Fetch next byte into MBR
– Perform multiway branch to the address in MBR at the beginning of
executing this instruction
Microinstruction branches to the microcode for executing the IJVM
instruction, and also begin fetching next byte: can be operand or next opcode
Please go through the instructions in 4.3.2
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Register Transfer Language (RTL)
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Can describe data path operations in RTL
A useful shorthand for describing R to R ops
– and actually all others
Same can be done for control logic
Everything comes from and goes to register!
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Thus every operation can be described as register transfers
 Therefore through combinational logic
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RTL Notation (pseudo-notation)
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Variables are (the contents of) registers
Operations are
– assignment (of a new value)
– arithmetic and logical operations
 etc.
Memory is a one dimensional array of a given length
– M[4] ( or R[4]) means location 4 of memory ( or register file)
Example of operation and assignment
– R[4]  R[4] + R[6]
(assignment stores into a register)
Conditional operation
– Z  1 (Z has value 1) if R[4] = 0
We may use RTL notations to describe simultaneous operations (in time)
– MDR  Mem[MAR] ; PC  PC + 2
 (these two operations are performed in parallel)
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RTL for a MOV instruction
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MAR  Ri (or Ri + displacement)
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Set the next address to read in memory as the contents of
the register Ri
MDR  Mem[MAR] when Dready=1
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When the signal Dready (Data Ready), store the contents
of the memory address MAR into the register MDR
Ri  MDR
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If we need the value in a specific register
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