Transcript Lecture Set 1

Computer Systems Organization: Lecture 1
Ankur Srivastava
University of Maryland, College Park
Adapted from Computer Organization and Design, Patterson & Hennessy, © 2005.”
Acknowledgement: Based on Slides By Mary Jane Irwin PSU
1
ENEE350
Spring07
Where is the Market?
Millions of Computers
1200
1122
1000
892
Embedded
Desktop
Servers
862
800
600
488
400 290
200
0
93
3
1998
2
114
3
1999
135
4
2000
129
4
2001
131
5
2002
ENEE350
Spring07
Performance (SPEC Int)
Processor
Performance
Increase
10000
DEC Alpha
DEC Alpha 21264A/667
21264/600
1000
100
10
SUN-4/260
1
1987
Intel Pentium
4/3000
Intel
Xeon/2000
DEC Alpha
DEC Alpha
DEC Alpha
5/500
4/266
DEC
5/300
IBM POWER
AXP/500
100
HP
IBM 9000/750
MIPS RS6000
MIPS M2000
M/120 1991
1989
1993
1995
1997
1999
2001
2003
Year
3
ENEE350
Spring07
DRAM
Capacity
Growth
1000000
Kbit capacity
100000
16
4M M
10000
512
256 M
128 M
64 M
M
1M
1000
256
K
64K
100
16K
10
1976 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002
Year of introduction
4
ENEE350
Spring07
Example Machine Organization
Computer
CPU
6
Memory
Devices
Control
Input
Datapath
Output
ENEE350
Spring07
Giving instructions to a Computer
• We ordinarily program in a high level language
like C, Java, would like to use human speech etc.
• Computers being digital machines understand the
language of 0 and 1.
• How do we translate from a high level language to
machine language
• How do computers take these instructions given in
machine language and execute them.
7
ENEE350
Spring07
Giving instructions to a Computer
High level Language
Compiler
Assembly Code
Assembler
Machine Code
8
ENEE350
Spring07
Giving instructions to a Computer
Computer understand the language of 0 and 1 but we
as programmers cannot code in them
Around 70S, assemblers were invented to translate so
called assemply code into machine code. Assembly
level code was a human readable instruction
sequence for the computer.
We will be disucssing the MIPS assembly code
9
ENEE350
Spring07
(vonNeumann) Processor Organization
•
Control needs to
CPU
Memory
Devices
1. input instructions from
Control
Input
Memory
2. issue signals to control the
Datapath
Output
information flow between the
Datapath components and to
Fetch
control what operations they
perform
Exec
Decode
3. control instruction sequencing
• Datapath needs to have the
– components – the functional units and
storage (e.g., register file) needed to execute instructions
– interconnects - components connected so that the instructions
can be accomplished and so that data can be loaded from and
10 stored to Memory
ENEE350
Spring07
Basic Datapath Organization
Registers
ALU
Memory
Registers are a bank of flip flops. Are expensive to
have in large numbers, therefore need to be
augmented by memory (DRAMS, SRAMS, DISKS)
11
ENEE350
Spring07
MIPS R3000 Instruction Set Architecture (ISA)
• Instruction Categories
– Computational
– Load/Store
– Jump and Branch
– Floating Point
• coprocessor
– Memory Management
– Special
R0 - R31
PC
HI
LO
Registers
3 Instruction Formats: all 32 bits wide
OP
rs
rt
OP
rs
rt
OP
12
rd
sa
immediate
jump target
funct
R format
I format
J format
ENEE350
Spring07
Example of MIPS Instruction
Add $t0, $s1, $s2
Sub $t0, $s1, $s2
destination  source1 op
source2
The operands and the final destination are MIPS Registers
13
ENEE350
Spring07