Transcript 5 - Faculty Web Sites

Assembly Language for Intel-Based
Computers, 4th Edition
Kip R. Irvine
Chapter 2: IA-32 Processor
Architecture
Slides prepared by Kip R. Irvine
Revision date: 09/25/2002
Modified by Dr. Nikolay Metodiev Sirakov
• Chapter corrections (Web) Assembly language sources (Web)
• Printing a slide show
(c) Pearson Education, 2002. All rights reserved. You may modify and copy this slide show for your personal use, or for
use in the classroom, as long as this copyright statement, the author's name, and the title are not changed.
Basic Microcomputer Design
• clock synchronizes CPU operations
• control unit (CU) coordinates sequence of execution steps
• ALU performs arithmetic and bitwise processing
data bus
registers
Central Processor Unit
(CPU)
ALU
CU
Memory Storage
Unit
I/O
Device
#1
I/O
Device
#2
clock
control bus
address bus
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
Web site
Examples
2
Clock
• synchronizes all CPU and BUS operations
• machine (clock) cycle measures time of a single
operation
• clock is used to trigger events
one cycle
1
0
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
Web site
Examples
3
Instruction Execution Cycle
PC
I-1
memory
op1
op2
fetch
read
registers
registers
write
I-1
write
Fetch
Decode
Fetch operands
Execute
Store output
instruction
register
decode
•
•
•
•
•
program
I-2 I-3 I-4
flags
ALU
execute
(output)
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
Web site
Examples
4
Multi-Stage Pipeline
• Pipelining makes it possible for processor to execute
instructions in parallel
• Instruction execution divided into discrete stages
Stages
S1
1
S2
S5
I-1
4
I-1
5
I-1
6
7
S6
I-1
3
Cycles
S4
I-1
2
Example of a nonpipelined processor.
Many wasted cycles.
S3
I-1
I-2
8
9
I-2
I-2
10
I-2
11
I-2
12
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
I-2
Web site
Examples
5
Pipelined Execution
• More efficient use of cycles, greater throughput of instructions:
Stages
Cycles
S1
1
I-1
2
I-2
3
4
5
S2
S3
S4
S5
S6
For k states and n
instructions, the
number of required
cycles is:
I-1
I-2
I-1
I-2
I-1
I-2
6
7
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
I-1
I-2
I-1
k + (n – 1)
I-2
Web site
Examples
6
Wasted Cycles (pipelined)
• When one of the stages requires two or more clock cycles, clock
cycles are again wasted.
Stages
Cycles
S1
S2
S3
exe
S4
1
I-1
2
I-2
I-1
3
I-3
I-2
I-1
I-3
I-2
I-1
I-3
I-1
4
5
6
I-2
7
I-2
8
I-3
9
I-3
10
S5
S6
For k states and n
instructions, the
number of required
cycles is:
I-1
I-1
k + (2n – 1)
I-2
I-2
I-3
11
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
I-3
Web site
Examples
7
Superscalar
A superscalar processor has multiple execution pipelines. In the
following, note that Stage S4 has left and right pipelines (u and v).
Stages
S4
Cycles
S1
S2
S3
u
v
S5
S6
1
I-1
2
I-2
I-1
3
I-3
I-2
I-1
4
I-4
I-3
I-2
I-1
I-4
I-3
I-1
I-2
I-4
I-3
I-2
I-1
I-3
I-4
I-2
I-1
I-4
I-3
I-2
I-4
I-3
5
6
7
8
9
10
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
For k states and n
instructions, the
number of required
cycles is:
k+n
I-4
Web site
Examples
8
Reading from Memory
•
Multiple machine cycles are required when reading from memory,
because it responds much more slowly than the CPU. The steps are:
• address placed on address bus
• Read Line (RD) set low
• CPU waits one cycle for memory to respond
• Read Line (RD) goes to 1, indicating that the data is on the data
bus
Cycle 1
Cycle 2
Cycle 3
Cycle 4
CLK
Address
ADDR
RD
Data
DATA
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
Web site
Examples
9
Cache Memory
• High-speed expensive static RAM both inside and
outside the CPU.
• Level-1 cache: inside the CPU
• Level-2 cache: outside the CPU
• Cache hit: when data to be read is already in cache
memory
• Cache miss: when data to be read is not in cache
memory.
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
Web site
Examples
10
How a Program Runs
User
sends program
name to
Operating
system
gets starting
cluster from
searches for
program in
returns to
System
path
loads and
starts
Directory
entry
Current
directory
Program
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
Web site
Examples
11
Multitasking
• OS can run multiple programs at the same time.
• Multiple threads of execution within the same
program.
• Scheduler utility assigns a given amount of CPU time
to each running program.
• Rapid switching of tasks
• gives illusion that all programs are running at once
• the processor must support task switching.
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.
Web site
Examples
12