Transcript MISP Exception Facility

MISP Exception Facility
Supported by SPIM simulator
Exception Handler
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The program while running in the system is call
usermode process
When CPU is processing the code of usermode
process, we call “the system is in the usermode”
The CPU running a usermode process may be
“interrupted” by exceptions or interrupt requests and
jump to a segment of code which is not part of the
program. That segment of code is called
exception/interrupt handlers.
Exception handler is in the “kernel”.
Kernel is a special memory area of the system
memory
Exception handler
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The location of exception handler in memory depends on system.
In MIPS machines (and SPIM simulator), we can replace the
default exception handler with a new exception handler for
handling exception and interrupts in our ways.
.ktext <address_of_exception_handler>
……..
our exception handler
……..
Microprocessor
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The microprocessor 0 is designed to fulfill 2 tasks below:
 Task 1: When an exception (or interrupt request) occurs, we need
to know information of the exception (interrupt request) in order to
handle it correctly.
 Task 2: Sometimes we need to disable/enable some particular
exceptions/interrupts
 For task 1, we consult Cause register to know information of
exception/interrupt that has just occurred. For task 2, we set/clear
some bits in the Status register
Registers of microprocessors are not registers of CPU. That is
we need to load registers of microprocessors to CPU’s register
(use mfc0 command), or load CPU register to microprocessor
register (mtc0 command)
Microprocessor’s registers
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Microprocessor 0 has several registers for various purposes.
Each register has a specific name (for the ease of description in human
language) and has a number (to use in assembly instruction)
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Cause register (number 13): after occurrence of an exception/interrupt,
Cause register holds information of the exception/interrupt.
Status register (number 12): Setting this register to a appropriate value can
control the way system react to exception/interrupt. That is we can
enable/disable interrupt or handler.
Count register (number 9): timer. It is periodically increased over time.
Compare register (number 11): when Count register equals to Compare
register, an timer interrupt occurs. We use this register to schedule next timer
interrupt.
BadVAddr, EPC, Config registers: they may not be necessary in this HW.
Format of Cause and Status register is in section A7, Appendix A
I/O: Memory-mapped console
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Console device supported by SPIM has 4 registers: Receiver
control, Receiver data, Transmitter control, and Transmitter data.
Each register of the console device is associated with an
address.
 Receiver control:
0xFFFF0000
 Receiver data:
0xFFFF0004
 Transmitter control:
0xFFFF0008
 Transmitter data:
0xFFFF000c
Writing to and reading from those registers is equivalent to
writing/reading to memory location specified by the address.
 For example: if you want to write to receiver control register, you
write to memory location 0xFFFF0000
Format of those 4 registers is in figure A.8.1, Appendix A
Interrupt handling example
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This program simply reads one key from
keyboard and echo it to the console then
exits
Source code http://cnlab.icu.ac.kr/~yhlee/CAspring2006/homeworks/example.s