3.1 Von Neunman ,Registers and Fetch Execute

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Transcript 3.1 Von Neunman ,Registers and Fetch Execute

Stored Program
• A stored-program digital computer is one that keeps its
programmed instructions, as well as its data, in read-write, random
access memory (RAM).
• The idea of the stored-program computer changed all that.
• By creating an instruction set architecture and detailing the
computation as a series of instructions (the program), the machine
becomes much more flexible.
• By treating those instructions in the same way as data, a storedprogram machine can easily change the program, and can do so
under program control.
• Once in the computers memory a program will be executed one
instruction at a time by repeatedly going through
• In the vast majority of modern computers, the same memory is used
for both data and program instructions.
• This is known as the stored program concept or sometimes the Von
Neumann principle.
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Von Neumann Architecture
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The von Neumann architecture is a
design model for a stored-program
digital computer that uses a processing
unit and a single separate storage
structure to hold both instructions and
data.
Memory is used to store both program
instructions and data
Program instructions are coded data
A central processing unit (CPU) gets
instructions and/or data from memory,
decodes the instructions and then
sequentially performs them.
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A processor fetches instructions and data
from a memory, operates on the data, and
writes the results back into memory
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It is named after the mathematician and
early computer scientist John von
Neumann.
Such computers implement a universal
Turing machine and have a sequential
architecture.
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Von Neumann Components
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Input
Output
Memory
ALU
Control Unit
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CPU
The processor itself consists of 3 main components:
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Arithmetic-logic unit (ALU)
in which all arithmetic and logic operations are carried out
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Control unit
coordinates the activities taking place in the CPU, memory and
peripherals
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System clock
generates clock pulses to step the control unit through its
operation
Also
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Registers
special storage locations to hold information temporarily
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System clock
• Electronic component
• It generates electric signals at a fast speed
• It controls all functions of computer using clock
ticks
• These ticks of system clock are known as clock
cycle and speed of CPU
• The speed at which the CPU executes
instructions is called clock speed or clock rate.
• It generates a continuous sequence of clock
pulse to step the control unit through its
operations
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Registers
• Is a small high speed memory inside CPU.
• Used to store temporary results
• CPU contains the no of registers and has
a predefined functions
• Register size determines how much
information it can store
• The size of register is in bytes
• A register can be one,two,four or eight
byte
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CPU Registers
Arithmetic
logic unit
Current
Instruction
Register (CIR)
R0
R1
General purpose
registers
R2
Program Counter
(PC)
R3
Status Register
(SR)
R4
R5
Control
Unit
Memory Address
Register (MAR)
Memory Data
Register
(MDR)
The MDR is sometimes
known as the memory
buffer register (MBR)
External bus
Main Memory
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Two internal registers
– Memory address register (MAR)
• Specifies the address for the next read or write
– Memory buffer register (MBR)
• Contains data written into memory or receives data
read from memory
– I/O address register
– I/O buffer register
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Top-Level Components
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Processor Registers
• User-visible registers
– Enable programmer to minimize mainmemory references by optimizing register use
• Control and status registers
– Used by processor to control operating of the
processor
– Used by privileged operating-system routines
to control the execution of programs
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User-Visible Registers
• Address Registers
– Index
• Involves adding an index to a base value to get an address
– Segment pointer
• When memory is divided into segments, memory is
referenced by a segment and an offset
• e.g. CS,DS,ES
– Stack pointer
• Points to top of stack
• Order is Last in first Out (LIFO)
• E.g. SP ,BP ,DI ,SI
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Control and Status Registers
• Program Counter (PC)
– Contains the address of an instruction to be fetched
• Instruction Register (IR)
– Contains the instruction most recently fetched
• Program Status Word (PSW)
– Condition codes
– Interrupt enable/disable
– Supervisor/user mode
• Condition Codes or Flags
– Bits set by the processor hardware as a result of operations
– Examples
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Positive result
Negative result
Zero
Overflow
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Others Registers
1. General Purpose registers:
• Available to the programmer and referenced in assembly
language programs
• Performing arithmetic functions
• Some computers there is one general purpose which is
accumulator
2. Stack Pointer (SP):
• Which points to a stack holding return addresses and is
accessed when an interrupt or break in sequential
program
3. Current instruction register (CIR):
• contain both the operator and operand of the current
instruction
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Working of Registers
There are several steps in the Fetch
Execute cycle that are executed in
order. The CPU goes through this cycle
once for each instruction that is
executed.
To start off the fetch cycle, the
address which is stored in the
program counter (PC) is
transferred to the memory
address register (MAR).
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Working of Registers
To finish the cycle, the newly fetched instruction is transferred to the
instruction register (IR) and unless told otherwise, the CU increments the
PC to point to the next address location in memory.
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Working of Registers
The CPU then transfers the instruction
located at the address stored in the
MAR to the memory buffer register
(MBR) via the data lines connecting the
CPU to memory.
The CPU then transfers the instruction
located at the address stored in the MAR
to the memory buffer register (MBR) via
the data lines connecting the CPU to
memory.
This transfer from memory to CPU is
coordinated by the control unit (CU).
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CU Operations
• Fetch : fetches the instruction from main
memory
• Decode: translate the program instruction
into commands that the computer can
process
• Execution: control the execution of
instruction
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Machine Cycle
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Fetch Instruction
Decode Instruction
Execute instruction
Storing
Process of writing the result to the
memory is called storing
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Instruction cycle in Processor
Control unit
ALU
(2) Decode
I-time
(1) Fetch
(3) Execute
E-time
Registers
(4) Store
Memory
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How the CPU registers are used
• Fetch phase :
• The address of next instruction
is copied from the PC to the
MAR.
• The instruction held at that
address is copied to the MDR
• The contents of the MDR are
copied to the CIR
• Execute Phase :
• The instruction held in the CIR
is decoded.
• The instruction is executed.
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Fetch Execute Cycle
No
No
Any
instructions
to execute?
Fetch next
instruction
Decode
instruction
Execute
instruction
Yes
Any
interrupts to
be
processed?
Yes
Start
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Transfer
control to
interrupt
handling
program
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Parallel Processors
Parallel processing is the ability of a computer system to undertake
more than one task simultaneously.
•Multiple processing elements in the system
• Need parallel programming to fully exploit such architectures.
• To achieve highest efficiency, the program characteristics
must match the underlying architecture.
•Newer computers no longer use the von Neumann
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architecture
Application of parallel processor
• Supercomputers utilizing parallel processing are
used to maintain the safety.
• Scientists are using parallel processing to
design computer-generated models of vehicles.
• Airlines use parallel processing to process
customer information, forecast demand and
decide what fares to charge.
• The medical community uses parallel processing
supercomputers.
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Advantages and
disadvantages
• Advantages:
– Memory is scalable with number of processors. Increase the
number of processors and the size of memory increases
proportionately.
– Each processor can rapidly access its own memory without
interference and without the overhead incurred with trying to
maintain cache
– Cost effectiveness: can use commodity, off-the-shelf
processors and networking
• Disadvantages:
– The programmer is responsible for the details associated
with data communication.
– It may be difficult to map existing data structures, based on
global memory, to this memory organization.
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