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Chapter 2 - The CRA-1
• Useful while learning OS basics to use a
reference computer system
• Book creates a Composite RISC
Architecture (CRA-1) computer system
(implicit homage to Cray-1? :)
• Simple organization: Figure 2.1
– CRA-1 CPU
• 32 general-purpose 32-bit registers, r0 through r31
• Note register usage on page 17
• CRA-1 CPU (continued)
• 9 control registers:
– ia = instruction address register (Program Counter)
– psw = program status word (1 bit for system/user mode; 1 bit
for interrupts enabled/disabled)
– base = per memory reference adder value
– bound = per memory reference upper bounds check
– iia = interrupt instruction address register; holds value of ia
before an interrupt is taken
– ipsw = interrupt program status word; holds value of psw
before an interrupt is taken
– ip = interrupt parameter register; info about last interrupt
– iva = interrupt vector address register; address of the
interrupt vector table (jump table)
– timer = interrupt timer register (autodecremented once every
µsecond); timer interrupt automatically occurs when timer
reaches 0
• CRA-1 CPU (continued)
– Processor supports dual-mode operation:
• System mode (bit 0 of psw = 0) - all instructions are
legal and all addresses are physical (base and bound
are not used)
• User mode (bit 0 of psw = 1) - instructions that
modify control registers are illegal; all addresses must
be less than bound and have base added to them
– Subset of instructions that are important to OS:
• Table 2.1 - note interesting ones:
–
–
–
–
–
loadAll
storeAll
move
syscall
rti
address ; load all 32 regs in one shot
address ; store all 32 regs in one shot
rM,rN ; move any reg to any other reg
; request sys service via S/W interrupt
; return from interrupt (restore psw, etc.)
• CRA-1 CPU (continued)
– Note use of asm directive to place in-line
assembly code in the middle of, say, C++ code:
SetTimer(int TimerValue) {
asm {
move timerValue,timer
}
}
• CRA-1 Memory
– byte-addressed machine
– 32-bit addresses
– Simple form of memory protection using base
and bound when in user mode; if either fails
program is aborted and ip is set to 2
• CRA-1 Memory
– Memory address space is from absolute address 0
to absolute address 0xEFFF FFFF
– I/O address space is from abs 0xF000 0000 to
0xFFFF FFFF
– Consider the machine to only have 16 MB, in
which case memory address is limited to abs
addresses 0 to 0xFF FFFF
• CRA-1 Interrupt Structure
– An interrupt is an immediate asynchronous
transfer of control caused by an event external to
the CPU
• Interrupt Structure (continued)
– Causes of interrupts:
•
•
•
•
System call (syscall instruction)
Timer expires (value of timer register reaches 0)
Disk I/O completed
Program performed an illegal operation:
– ip = 0 : attempted to execute an undefined instruction
– ip = 1 : attempted to execute a system instruction while in
user mode
– ip = 2 : address out of bounds while in user mode (address is
less than base or greater than bound)
• Interrupt Structure (continued)
• CRA-1 Interrupt Handling - when one of the four
types of interrupts occurs the following steps are taken
(ref. Table 2.2 for interrupt vector table):
– ipsw <- psw (save current program state)
– psw <- 0 (set to system mode; disable future interrupts)
– ip <- interrupt parameter (if appropriate, e.g. - program
error)
– iia <- ia (save current execution address)
– ia <- (interruptNumber * 4) + iva (control passes to the
appropriate interrupt routine via the interrupt vector table)
• After the interrupt handler routine is done, it issues the
rti instruction, which returns control & state to the
point of execution prior to the interrupt
– ia <- iia
– psw <- ipws
– Restore any regs that may have been used
• Interrupt Structure (continued)
– If bit 1 of psw = 0, interrupts are masked
(recorded but not taken until interrupts are reenabled)
– Only the Timer and Disk interrupts are maskable;
the SysCall and ProgramError interrupts are
unmaskable (will always generate an interrupt)
– The Timer interrupt has a higher priority than the
Disk interrupt
– Note that the CRA-1 interrupt structure, while
providing enough structure to demonstrate the
intimate relationship between hardware and the
OS, is pretty simplistic given most computers
• CRA-1 I/O Devices
– Memory-mapped I/O vs Explicit I/O instructions
– Program writes I/O instructions to specific
memory locations and reads other specific
memory addresses to receive information from
I/O devices
– CRA-1 has one disk controller with one hard disk
drive
– Disk drive has 4,096-byte blocks (aka sectors)
– Two I/O commands for disk controller: read
block and write disk block
– Note OS-style C++ code using memory-mapped
I/O in Figure 2.2; Chapter 14 has an excellent
quick overview of “real world” I/O devices