Transcript View File - University of Engineering and Technology, Taxila

Computer Architecture &
Organization
Instructions: Language of Computer
Engr. Umbreen Sabir
Computer Engineering Department,
University of Engg. & Technology Taxila.
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30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
Introduction
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Instructions:
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Instruction Set:
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The vocabulary of commands understood by a given
architecture.
Stored Program Concept:
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The words of a computer language.
The idea that instructions and data of many types can be
stored in memory as numbers, leading to the stored program
computer.
30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
Operations of Computer Hardware
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Every computer must be able to perform
arithmetic.
MIPS assembly language notation
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Notation is rigid. Every instruction must follow
this format.
To perform operation.
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add a, b, c
Add two variables b and c and put sum in a.
a=b+c+d+e
add a, b, c
# The sum of b & c is placed in a.
add a, a, d
# The sum of b, c & d is now in a.
add a, a, e
# The sum of b, c, d & e is now in a.
30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
Operations of Computer Hardware
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# indicates comments.
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Every instruction should have three
operands.
Hardware for variable number of
operands is more complicated.
Design principle # 1:
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Comments always terminate at the end of line.
Simplicity favors regularity.
30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
Example # 1
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C statements are:
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Translation from C to MIPS assembly is
performed by compiler.
Assembly code will be:
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a= b + c
d= a - e
add a, b, c
sub d, a, e
30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
Example # 2
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C statement is:
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Assembly code will be:
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f = (g + h) + (I + j)
add t0, g, h
add t1, I, j
sub f, t0, t1
30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
Operands of Computer Hardware
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Operands are restricted and must come from
registers.
Registers:
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MIPS registers are 32 32-bit.
Design principle # 2:
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Primitives used in hardware design that are also
visible to the programmer.
Smaller is faster.
30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
MIPS Register File
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Holds thirty-two
32-bit registers
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Two read ports and
One write port
Register File
32 bits
src1 addr
src2 addr
dst addr
write data
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32 src1
data
5
5
32
32
locations
32 src2
data
write control
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30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
Operands of Computer Hardware
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Large no. of registers will increase clock cycle
time.
MIPS instruction is 32-bit long.
In MIPS, register notation is:
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Two character name followed by a dollar sign.
$s1, $s2,….. For register that correspond to C and
Java variables.
$t0, $t1,…. For temporary registers.
30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
Example # 3
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C statement is:
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Variables f, g, h, I and j are in registers $t0,
$s1, $s2, $s3 and $s4 respectively.
Assembly code will be:
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f = (g + h) + (I + j)
add $t0, $s1, $s2
add $t1, $s3, $s4
sub $s0, $t0, $t1
30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
Memory Operands
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Processor can keep small amount of data in
registers.
For arrays and structures memory is used.
Arithmetic operations occur only on registers.
So data transfer instructions are used.
Data transfer instructions are:
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Load -> copies data from memory to registers.
Store-> stores data from register to memory.
Format-> name of operation followed by register to be
loaded/stored, then a constant and register used to access
memory.
Sum of constant and contents of second register gives
memory address.
30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
Example # 4
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C statement is:
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Base address of array A is in $s3. So the
address is $s3 + number to select element 8.
Constant is offset & register is base address.
Assembly code will be:
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g = h + A[8]
lw $t0, 8($s3)
add $s1, $s2, $t0
30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
Load Instruction
op
rs
rt
16 bit offset
Memory
2410 + $s2 =
0xf f f f f f f f
0x120040ac
$t0
. . . 0001 1000
+ . . . 1001 0100
$s2
. . . 1010 1100 =
0x120040ac
0x12004094
data
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30/01/2009
0x0000000c
0x00000008
0x00000004
0x00000000
word address (hex)
CA&O Lecture 02 by Engr. Umbreen Sabir
Memory Operands
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Since 8-bit bytes are so useful, most architectures
address individual bytes in memory
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The memory address of a word must be a multiple of 4
(alignment restriction)
Big Endian:
leftmost byte is word address
IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA
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Little Endian:
rightmost byte is word address
Intel 80x86, DEC Vax, DEC Alpha (Windows NT)
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Alignment restriction-> Words must start at
addresses that are multiples of 4.
30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
Memory Operands
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Byte addressing affect array index.
Offset added to $s3 in previous example
will be 4*8, or 32.
Process of putting less commonly used
variables in memory is called spilling
registers.
little endian byte 0
3
2
1
0
msb
15
lsb
0
big endian byte 0
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CA&O Lecture 02 by Engr. Umbreen Sabir
Example # 5
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C statement is:
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Base address of array A is in $s3.
Assembly code will be:
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A[12]= h + A[8]
lw $t0, 32($s3)
add $t0, $s2, $t0
sw $t0 48($s3)
30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
Constant or Immediate Operands
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Constants are used in instructions for certain
operations. E.g. to increment an index.
Add instruction with constant is:
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Design principle # 3
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addi $s3, $s3, 4 # s3= s3 + 4
Make the common case fast.
30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
MIPS Immediate Instructions
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Small constants are used often in typical
code
Possible approaches?
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put “typical constants” in memory and load them
create hard-wired registers (like $zero) for
constants like 1
have special instructions that contain constants !
30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
MIPS Immediate Instructions
addi $sp, $sp, 4 #$sp = $sp + 4
slti $t0, $s2, 15 #$t0 = 1 if $s2<15
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Machine format (I format):
op
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rt
16 bit immediate
I format
The constant is kept inside the instruction
itself!
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rs
Immediate format limits values to the range
+215–1 to -215
30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
MIPS Register Convention
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30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
MIPS Instruction Format
OP
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rs
rt
rd
shamt
funct
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Op-> 6-bits opcode that specifies the operation
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rs-> 5-bits register address of 1st source operand
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rt-> 5-bits register address of second source operand
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Rd-> 5-bits register file address of the result’s
destination
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Shamt-> 5-bits shift amount (for shift instructions)
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Funct-> 6-bits function code.
30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
MIPS Instruction Format
3 Instruction Formats: all 32 bits wide
OP
rs
rt
OP
rs
rt
OP
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sa
funct
immediate
R format
I format
J format
jump target
Design principle # 4
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rd
Good design demands good compromises.
30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
Example # 6
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Convert in machine language.
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A[300] = h + A[300].
Lw $t0, 1200($t1)
Lw $t0, $s2, $t0
Sw $t0, 1200($t1).
30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
Loading and Storing Bytes
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MIPS provides special instructions to move
bytes
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Lb $t0,1($s3) #load byte 4m memory
Sb $t0,6($s3) #store byte to memory
load byte places the byte from memory in the rightmost 8 bits of
the destination register
store byte takes the byte from the rightmost 8 bits of a register
and writes it to a byte in memory
- what happens to the other bits in the memory word?
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30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
Logical Operations
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Shift left-> sll
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Shifting left by ‘i’ bits gives same result as by
multiplying by 2i
Shift right-> srl
Bit-by-bit AND-> and, andi
Bit-by-bit OR-> or, ori
Bit-by-bit NOT nor
30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir
Next Lecture and Reminders
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Next lecture
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MIPS ISA Review
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Reading assignment – Chapter 2
30/01/2009
CA&O Lecture 02 by Engr. Umbreen Sabir