Transcript Computer Organization

6. Basic Machine Organizaton
6.2 Computer Organization
Computer Studies
(Advanced Level)
Computer Organization
A computer has no intelligence. It follows the
commands you specify in the program.
Program:
A sequence of instructions.
The CPU executes them one-by-one.
Programming Language
Machine-Level:
used by the computer
trains of 0’s and 1’s
Assembly level source code -> assemble -> object
code
High-Level and Mid-Level
Nearer to natural language
Need compilation
Source code -> compile -> object code
Why Assembly Language? (1)
Machine program is difficult to write, debug,
understand and error-prone.
Use symbols or mnemonics to replace the 0’s
and 1’s. E.g.:
assembly
: MOV A, 1
machine
: 0011 0101 0001
Using machine language, one has to determine the
address of “A” manually.
Why Assembly Language? (2)
Using Assembly Language, you need an
assembler to translate an assembly program to
a machine program.
Assembly Language
1-1 correspondence with the machine program.
Directly communicates with the computer
has precise control of the computer
machine dependent
Computer Architecture
Memory (RAM,
ROM)
Control
Data
Address
Processor
I/O
Unit
Disk
Modern CRT
terminal
Keyboard
Processor
ALU (Arithmetic Logic Unit)
system clock
registers
Instruction register(IR)
Instruction decoder(ID)
internal system bus
Bus and register
Control
Data
Address
Controller
(System Clock)
System
Bus
MDR
(Data Buffer)
ID
CCR
Instruction
Register(IR)
ALU
Internal Bus
MAR
(Address Buffer)
Registers
Program counter
(PC)
Basic Instruction Formats
An instruction is divided into different fields:
Opcode | Operand 1 | … | Operand N
Opcode: Operation to perform, e.g. addition
Operand 1 to Operand N: The data which the
operation will act on.
Basic Instruction Formats
 The number of operands N varies for different computers. In
8088, N can be 0, 1, or 2.
 N=2:
E.g. “ADD AX, BX” means “AX<-(AX)+(BX)”
Note: “(AX)” means the content of the register “AX”
 N=1:
e.g. “PUSH AX” means “Stack <- (AX)”
 N=0:
e.g. “RET means return from procedure
Instruction Execution Cycle
1. Instruction Fetch
a) The address of the current instruction to execute is stored in a CPU’s
internal register called the Program Counter (PC). (much like a
“pointer” to point at the next instruction)
b) Put this address into Memory Address Register (MAR) and initiates
a Read Cycle.
C) The instruction is read into another CPU’s internal register called
the Memory Data Register (MDR).
D) the data in MDR is then forwarded to the Instruction Register (IR)
via the internal bus.
Note: MAR = Address Buffer, MDR = data buffer
Instruction Fetch
 e) at the same time, PC is incremented to point at the next
instruction:
PC------->
1003
1007
1009
…
1033
ADD AH, 2 Current
JL TARGET Next
…
…
…
TARGET
Notes of Instruction Fetch
Note:
Increment PC by how much?
It depends on the size of the current instruction
(what if irregular)
Assume the next instruction follows the
current instruction. (What if we have a branch
instruction? E.g.if (A>0)…else…
Instruction execution cycle
2. Instruction Decode:
Generate the control signals to accomplish the
tasks of the instruction.
3. Data Fetch (for operands)
Instruction Fetch - Execution
4. Execution:
ALU
Set the condition codes (flags) to indicate the
characteristics of last execution’s result.
E.g. overflow, negative
Execution
Note:
Condition Code Register (CCR) is more
commonly known as the Processor Status Word
(PSW)
Branch instructions check the status of the PSW
A branch is either taken or not taken. If it is taken,
the branch address is loaded into the PC.
Effectively, the sequential flow of instruction (or
control) is interrupted.
E.g.1
Control
Data
Address
Controller
(System Clock)
System
Bus
MDR
(Data Buffer)
ID
CCR
Instruction
Register(IR)
ALU
Internal Bus
MAR
(Address Buffer)
Registers
PC: 1003
E.g.1
Control
Data
Address
Controller
(System Clock)
System
Bus
MDR
(Data Buffer)
ID
CCR
Instruction
Register(IR)
ALU
Internal Bus
MAR
1003
Registers
PC: 1007
E.g.1
Control
Data
Address
Controller
(System Clock)
System
Bus
MDR
ADD AH, 2
ID
CCR
Instruction
Register(IR)
ALU
Internal Bus
MAR
1003
Registers
PC: 1007
E.g.1
Control
Data
Address
Controller
(System Clock)
System
Bus
MDR
ADD AH, 2
ID
CCR
IR:
ADD AH, 2
ALU
Internal Bus
MAR
1003
Registers
PC: 1007
E.g.1
Control
Data
Address
Controller
(System Clock)
ID
IR:
ADD AH, 2
System
Bus
MDR
ADD AH, 2
CCR: -ve
ALU
Internal Bus
MAR
1003
Registers
PC: 1007
E.g.1
Control
Data
Address
System
Bus
Controller
(System Clock)
ID
IR:
ADD AH, 2
MDR
ADD AH, 2
CCR: -ve
ALU
Internal Bus
MAR
1007
Registers
PC: 1009
E.g.1
Control
Data
Address
System
Bus
Controller
(System Clock)
ID
IR:
ADD AH, 2
MDR:
JL TARGET
CCR: -ve
ALU
Internal Bus
MAR
1007
Registers
PC: 1009
E.g.1
Control
Data
Address
System
Bus
Controller
(System Clock)
ID
IR:
JR TARGET
MDR:
JL TARGET
CCR: -ve
ALU
Internal Bus
MAR
1007
Registers
PC: 1009
E.g.1
Control
Data
Address
System
Bus
Controller
(System Clock)
ID
IR:
JR TARGET
MDR:
JL TARGET
CCR: -ve
ALU
Internal Bus
MAR
1007
Registers
PC: 1033
E.g.2
PC------->
1003
1007
1009
1033
1063
MOV AH, SRC Current
JL TARGET
Next
…
…
20
TARGET
SRC
E.g.2
Control
Data
Address
System
Bus
Controller
(System Clock)
MDR
MOV AH, SRC
ID
CCR
Instruction
Register(IR)
ALU
Internal Bus
MAR
1003
Registers
PC: 1007
E.g.2
Control
Data
Address
System
Bus
Controller
(System Clock)
MDR
MOV AH, SRC
ID
CCR
IR:
MOV AH, SRC
ALU
Internal Bus
MAR
1003
Registers
PC: 1007
E.g.2
Control
Data
Address
System
Bus
Controller
(System Clock)
MDR
MOV AH, SRC
ID
CCR
IR:
MOV AH, SRC
ALU
Internal Bus
MAR
1063
Registers
PC: 1007
E.g.2
Control
Data
Address
System
Bus
Controller
(System Clock)
MDR:
20
ID
CCR
IR:
MOV AH, SRC
ALU
Internal Bus
MAR
1063
Registers
PC: 1007