Transcript Instructions

Overview of
Microprocessors
Lecturer: Sri Parameswaran
Notes by : Annie Guo
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Lecture overview



Introduction to microprocessors
Instruction set architecture
Typical commercial microprocessors
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Microprocessors


A microprocessor is a CPU on a single chip.
If a microprocessor, its associated support
circuitry, memory and peripheral I/O
components are implemented on a single
chip, it is a microcontroller.

We use AVR microcontroller as the example in
our course study
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Microprocessor types

Microprocessors can be characterized based
on

the word size


Instruction set structure


RISC (Reduced Instruction Set Computer), CISC
(Complex Instruction Set Computer)
Functions


8 bit, 16 bit, 32 bit, etc. processors
General purpose, special purpose such image
processing, floating point calculations
And more …
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Typical microprocessors

Most commonly used

68K


x86

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Advanced RISC Machine
PowerPC


Microprocessor without interlocked pipeline stages
ARM


Intel
MIPS


Intel
IA-64


Motorola
Apple-IBM-Motorola alliance
Atmel AVR
A brief summary will be given later
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Microprocessor applications

A microprocessor application system can be
abstracted in a three-level architecture

ISA is the interface between hardware and software
FORTRAN 90
program
C program
FORTRAN 90
program compiled
to ISA program
C program
compiled
to ISA program
ISA level
Software
Hardware
ISA program executed
by hardware
Hardware
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ISA



Stands for Instruction Set Architecture
Provides functional specifications for software
programmers to use/program hardware to
perform certain tasks
Provides the functional requirements for
hardware designers so that their hardware
design (called micro-architectures) can
execute software programs.
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What makes an ISA

ISA specifies all aspects of a computer
architecture visible to a programmer

Basic

Instructions






Instruction format
Addressing modes
Native data types
Registers
Memory models
advanced

Interrupt handling

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To be covered in the later lectures
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Instructions

This is the key part of an ISA


specifies the basic operations available to a
programmer
Example:


Arithmetic instructions
Instruction set is machine oriented

Different machine, different instruction set

For example

68K has more comprehensive instruction set than ARM
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Instructions (cont.)

Instruction set is machine oriented

Same operation, could be written differently in
different machine

AVR



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Addition: add r2, r1
;r2  r2+r1
Branching: breq 6 ;branch if equal condition is true
Load:
ldi r30, $F0
;r30  Mem[F0]
68K:



Addition:
add d1,d2
;d2  d2+d1
Branching: breq 6 ;branch if equal condition is true
Load:
mov #1234, D3
;d3  1234
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Instructions (cont.)

Instructions can be written in two languages
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Machine language

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
made of binary digits
Used by machines
Assembly language
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
a textual representation of machine language
Easier to understand than machine language
Used by human beings
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Machine code vs. assembly
code

There is a one-to-one mapping between the
machine code and assembly code

Example (Atmel AVR instruction):
For increment register 16:
 1001010100000011 (machine code)
 inc r16
(assembly language)

Assembly language also includes directives
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Instructions to the assembler
Example:
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.def temp = r16
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.include “mega64def.inc”
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Data types
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The basic capability of using different classes of values.
Typical data types
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Numbers
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Integers of different lengths (8, 16, 32, 64 bits)


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Floating point numbers, e.g. 32 bits (single precision) or 64 bits
(double precision)


Available in some processors such as PowerPC
BCD (binary coded decimal) numbers


Possibly signed or unsigned
Commonly available
Available in some processors, such as 68K
Non-numeric


Boolean
Characters
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Data types (cont.)

Different machines support different data
types in hardware

e.g. Pentium II:
Data Type
Signed integer
Unsigned integer
BCD integer
8 bits



16 bits


Floating point

32 bits


64 bits


128 bits
e.g. Atmel AVR:
Data Type
Signed integer
Unsigned integer
BCD integer
Floating point
8 bits


16 bits
Partial
Partial
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32 bits
64 bits
128 bits
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Registers
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Two types
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General purpose
Special purpose
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Used for special functions
e.g.

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Program Counter (PC)
Status Register
Stack pointer (SP)
Input/Output Registers
Stack pointer and Input/Output Registers will be
discussed in detail later.
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General Purpose Registers
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A set of registers in the machine
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Used for storing temporary data/results
For example
 In (68K) instruction add d3, d5, operands are stored in
general registers d3 and d5, and the result are stored in d5.
Can be structured differently in different machines

For example
 Separated general purpose registers for data and address


68K
Different numbers registers and different size of each
registers


32 32-bit in MIPS
16 32-bit in ARM
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Program counter
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Special register
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Can be of different size

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For storing memory address of currently executed
instruction
E.g. 16 bit, 32 bit
Can be auto-incremented


By the instruction word size
Gives rise the name “counter”
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Status register
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Contains a number of bits with each bit
associated with CPU operations
Typical status bits

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V: Overflow
C: Carry
Z: Zero
N: Negative
Used for controlling program execution flow
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Memory models
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Data processed by CPU is usually large and cannot
be held in the registers at the same time.
Both data and program code need to be stored in
memory.
Memory model is related to how memory is used to
store data
Issues
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Addressable unit size
Address spaces
Endianness
Alignment
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Addressable unit size
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Memory has units, each of which has an
address
Most common unit size is 8 bits (1 byte)
Modern processors have multiple-byte unit
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For example:

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32-bit instruction memory in MIPs
16-bit Instruction memory in AVR
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Address spaces
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The range of addresses a processor can
access.

The address space can be one or more than one
in a processor. For example

Princeton architecture or Von Neumann architecture

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A single linear address space for both instructions and data
memory
Harvard architecture

Separate address spaces for instructions and data
memories
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Address spaces (cont.)

Address space is not necessarily just for
memories

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E.g, all general purpose registers and I/O
registers can be accessed through memory
addresses in AVR
Address space is limited by the width of the
address bus.

The bus width: the number of bits the address is
represented
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Endianness
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Memory objects
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Memory objects are basic entities that can be
accessed as a function of the address and the
length
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E.g. bytes, words, longwords
For large objects (>byte), there are two
ordering conventions

Little endian – little end (least significant byte)
stored first (at lowest address)
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
Intel microprocessors (Pentium etc)
Big endian – big end stored first
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SPARC, Motorola microprocessors
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Endianness (cont.)

Most CPUs produced since ~1992 are
“bi-endian” (support both)


some switchable at boot time
others at run time (i.e. can change dynamically)
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Big Endian & Little Endian
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Example: 0x12345678—a long word of 4
bytes. It is stored in the memory at address
0x00000100


big endian:
little endian:
Address
0x00000100
0x00000101
0x00000102
0x00000103
data
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56
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Address
0x00000100
0x00000101
0x00000102
0x00000103
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data
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56
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Alignment
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Often multiple bytes can be fetched from
memory
Alignment specifies how the (beginning)
address of a multiple-byte data is determined.

data must be aligned in some way. For example



4-byte words starting at addresses 0,4,8, …
8-byte words starting at addresses 0, 8, 16, …
Alignment makes memory data accessing
more efficient
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Example

A hardware design that has data fetched from
memory every 4 bytes

Fetching an unaligned data (as shown)
means to access memory twice.
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Instruction format
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Is a definition


how instructions are represented in binary code
Instructions typically consist of

Opcode (Operation Code)


Operands


defines the operation (e.g. addition)
what’s being operated on
Instructions typically have 0, 1, 2 or 3
operands
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Instruction format examples
OpCode
OpCode
Opd1
OpCode
Opd2
OpCode Opd1
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Opd
Opd2 Opd3
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Example (AVR instruction)
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Subtraction with carry
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Syntax: sbc Rd, Rr
Operation: Rd ← Rd – Rr – C
Rd: Destination register. 0  d  31
Rr: Source register. 0  r  31, C: Carry
Instruction format
0 0 0 0
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

1 0 r d
d d d d
r r r r
0
OpCode uses 6 bits (bit 9 to bit 15).
Two operands share the remaining 10 bits.
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Instruction lengths


The number of bits an instruction has
For some machines – instructions all have
the same length

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E.g. MIPS machines
For other machines – instructions can have
different lengths

E.g. M68K machine
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Instruction encoding

Operation Encoding


2n operations needs at least n bits
Operand Encoding

Depends on the addressing modes and access
space.


For example: An operand in direct register addressing
mode requires at most 3 bits if the the number of
registers it can be stored is 8.
With a fixed instruction length, more encoding
of operations means less available bits for
encoding operands

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Tradeoffs should be concerned
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Example 1
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A machine has:



16 bit instructions
16 registers (i.e. 4-bit register addresses)
Instructions could be formatted like this:
OpCode


Operand1
Operand2
Operand3
Maximally 16 operations can be defined.
But what if we need more instructions and some
instructions only operate on 0, 1 or 2 registers?
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Example 2

For a 16 bit instruction machine with 16
registers, design OpCodes that allow for




14 3-operand instructions
30 2-operand instructions
30 1-operand instructions
32 0-operand instructions
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Addressing modes


Instructions need to specify where to get operands from
Some possibilities


Values are in the instruction
Values are in the register


Register number is in the instruction
Values are in memory


address is in instruction
address is in a register


address is register value plus some offset



register number is in the instruction
register number is in the instruction
offset is in the instruction (or in a register)
These ways of specifying the operand locations are called
addressing modes
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Immediate Addressing

The operand is from the instruction itself


I.e the operand is immediately available from the
instruction
For example, in 68K
addw


#99, d7
Perform d7  99 + d7; value 99 comes from the
instruction
d7 is a register
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Register Direct Addressing


Data from a register and the register number
is directly given by the instruction
For example, in 68K
addw


d0,d7
Perform d7  d7 + d0; add value in d0 to value in d7
and store result to d7
d0 and d7 are registers
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Memory direct addressing



The data is from memory, the memory
address is directly given by the instruction
We use notion: (addr) to represent memory
value with a given address, addr
For example, in 68K
addw

0x123A, d7
Perform d7  d7 + (0x123A); add value in memory
location 0x123A to register d7
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Memory Register Indirect
Addressing


The data is from memory, the memory
address is given by a register and the register
number is directly given by the instruction
For example, in 68K
addw

(a0),d7
Perform d7  d7 + (a0); add value in memory
with the address stored in register a0, to register
d7

For example, if a0 = 100 and (100) = 123, then this
adds 123 to d7
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Memory Register Indirect
Auto-increment

The data is from memory, the memory
address is given by a register, which is
directly given by the instruction; and the value
of the register is automatically increased – to
point to the next memory object.


Think about i++ in C
For example, in 68K
addw

(a0)+,d7
d7  d7 + (a0); a0  a0 + 2
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Memory Register Indirect
Auto-decrement

The data is from memory, the memory
address is given by a register and the register
number is directly given by the instruction;
but the value of the register is automatically
decreased before such an operation.


Think --i in C
For example, in 68K
addw

-(a0),d7
a0  a0 –2; d7  d7 + (a0);
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Memory Register Indirect with
Displacement

Data is from the memory with the address
given by the register plus a constant


Used in the access of a member in a data
structure
For example, in 68K
addw

a0@(8), d7
d7  (a0+8) +d7
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Address Register Indirect with
Index and displacement

The address of the data is sum of the initial address
and the index address as compared to the initial
address plus a constant


Used in accessing element of an array
For example, in 68K
addw


a0@(d3)8, d7
d7  (a0 + d3+8)
With a0 as an initial address and d3 as an index
dynamically pointing to different elements, plus a constant
for a certain member in an array element.
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RISC

RICS stands for reduced instruction set
computer

Smaller and simpler set of instructions


Smaller: small number of instructions in the instruction
set
Simpler: instruction encoding is simple


Such as fixed instruction length
All instructions take about the same amount of
time to execute
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CISC

CISC stands for complex instruction set
computer

Each instructions can execute several low-level
operations



Such operations of load memory, arithmetic and store
memory in one instructions
Required complicated hardware support
All instructions take different amount of time to
execute
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Recall: Typical processors

Most commonly implemented in hardware







68K
 Motorola
x86
 Intel
IA-64
 Intel
MIPS
 Microprocessor without interlocked pipeline stages
ARM
 Advanced RISC Machine
PowerPC
 Apple-IBM-Motorola alliance
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Atmel AVR
46
X86

CISC architecture





16 bit  32-bit  64-bit
Words are stored in the little endian order
Allow unaligned memory access.
Current x86-processors employs a few “extra”
decoding steps to (during execution) split (most) x86
instructions into smaller pieces (micro-instructions)
which are then readily executed by a RISC-like
micro-architecture.
Application areas (dominant)

Desktop, portable computer, small servers
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68K

CISC processor





Early generation, hybrid 8/16/32 bit chip (8-bit
bus)
Late generation, fully 32-bit
Separate data registers and address registers
Big endian
Area applications


Early used in for calculators, control systems,
desktop computers
Later used in microcontroller/embedded
microprocessors.
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MIPS

RISC processor



A large family designs with different configurations
Deep pipeline (>=5 stages)
With additional features




Clean instruction set
Could be booted either big-endian or little-endian
Many application areas, including embedded
systems
The design of the MIPS CPU family, together with
SPARC, another early RISC architecture, greatly
influenced later RISC designs
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ARM

32-bit RISC processor






Three-address architecture
No support for misaligned memory accesses
16 x 32 bit register file
Fixed opcode width of 32 bit to ease decoding and
pipelining, at the cost of decreased code density
Mostly single-cycle execution
With additional features

Conditional execution of most instructions



reducing branch overhead and compensating for the lack of
a branch predictor
Powerful indexed addressing modes
Power saving
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PowerPC




Superscalar RISC
32-bit, 64-bit implementation
With both big-endian and little endian modes,
can switch from one mode to the other at runtime.
Intended for high performance PC, for highend machines
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Reading Material

Chap.2 in Microcontrollers and
Microcomputers.
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Questions
1. Given an address bus width in a
processor as 16-bit, determine the
maximal address space.
2. Assume a memory address is 0xFFFF,
how many locations this address can
represent if the related computer is?
I) a Harvard machine
II) a Von Neumann machine
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