Transcript 2 nd half - Department of Computer Science and Information Systems

Introduction to Computer Systems
Lecturer: Steve Maybank
Department of Computer Science and Information Systems
[email protected]
Autumn 2015
Week 5b: Types of Instruction
27 October 2015
Birkbeck College, U. London
1
Machine Architecture
Main memory
Central processing unit
Arithmetic/
Registers
logic
0
unit
1
00
Program counter
.
.
Control
unit
Address | Cells
Bus
Instruction register
F
27 October 2015
Brookshear, Section 2.2
01
.
.
FF
2
Machine Language Concepts






Registers (R, S, T…)
Memory addresses
Number of bytes in a memory cell
Instruction
Sequence of instructions
Branching (choice of next instruction)
27 October 2015
Brookshear, Section 2.2
3
Properties of the Illustrative Machine






No.
No.
No.
No.
No.
No.
memory cells: 256
bits in a memory cell: 8 (1 byte)
registers: 16
bits in a register: 8 (1 byte)
bits in the programme counter: 8 (1 byte)
bits in the instruction register: 16 (2 bytes)
27 October 2015
Birkbeck College, U. London
4
Illustrative Machine Language
Op-code Operand
1
2
3
4
5
RXY
RXY
RXY
0RS
RST
6
RST
27 October 2015
description
LOAD R from memory location XY
LOAD R with the bit pattern XY
STORE R at memory location XY
Move bit pattern in R to S
Add (2s comp) contents of S,T. Put
result in R
Add (fp) contents of S,T.Put result in R
Brookshear, Appendix C
5
Illustrative Machine Language
Op-code Operand
7
8
9
A
B
RST
RST
RST
R0X
RXY
C
000
27 October 2015
Description
OR contents of S, T. Put result in R
AND contents of S, T. Put result in R
XOR contents of S, T. Put result in R
Rotate right contents of R for X times.
If contents R=contents register 0, then
jump to instruction at address XY,
otherwise continue as normal.
Halt
Brookshear, Appendix C
6
Types of Instruction



Data transfer
LOAD, STORE, MOVE
Arithmetic/Logic
ADD, OR, AND, XOR, ROTATE
Control
JUMP, HALT
27 October 2015
Brookshear, Section 2.2
7
Format of an Instruction



Instruction=op-code field+operand field
Op-code: identifies the elementary
operation, e.g. STORE, SHIFT, XOR,
JUMP.
Operand: additional information, e.g.
data or a register address.
27 October 2015
Brookshear, Section 2.2
8
Instruction 156C
1
Op-code 1: load
Register with bit
pattern in memory
at the given
address
27 October 2015
5
6
C
memory address
register
Brookshear, Section 2.3
9
Op Code 7 (OR)
1
0
0
1
1
1
0
1
1st register
0
1
1
1
2nd register
1
1
1
1
3rd register
OR
0
0
0
1
=
1
0
27 October 2015
0
1
Brookshear, Section 2.3
10
Op Code A (Rotate right)
1
0
0
1
1
1
0
1
register
1
1
0
0
1
1
1
0
rotate right 1
0
1
1
0
0
1
1
1
rotate right 2
27 October 2015
Brookshear, Section 2.3
11
Instruction B258
B
2
Op-code B: change value
of program counter if
contents of indicated
register = contents of
register 0
5
Indicated
register
8
New contents
of program
counter
Brookshear, Fig. 2.9.
27 October 2015
Brookshear, Section 2.3
12
Translate into Machine Language
1.
2.
3.
Load register number 3 with the hexadecimal
value 56
Rotate register number 5 three bits to the right
AND the contents of register A with the
contents of register 5 and leave the result in
register 0
25 October 2015
Brookshear, Section 2.2
13
Machine Cycle
Fetch next instruction
from memory to the
CPU
Fetch
Decode
Execute
27 October 2015
Decode the
instruction
Execute the
instruction
Brookshear, Section 2.3
14
First Part of the Fetch Step of the Machine Cycle
Main memory
CPU
address
program counter
A0
bus
instruction register
156C
27 October 2015
Brookshear, Section 2.3
A0
cells
15
A1
6C
A2
16
A3
6D
15
Completion of the Fetch Step
Main memory
CPU
address
program counter
A2
bus
instruction register
156C
27 October 2015
Brookshear, Section 2.3
A0
cells
15
A1
6C
A2
16
A3
6D
16
Updating the Program Counter




Fixed length instructions (2 bytes).
Instructions stored consecutively in main
memory.
Each memory cell holds 1 byte.
Then pc pc + 2 at the end of each Fetch.
memory
…5 6
7
8
9
10 11 12 13 14 …
pc=7
27 October 2015
Brookshear, Section 2.3
17
Example
The machine is
started with 00 in the
program counter.
Describe the actions
of the CPU if the
memory contains the
following bit patterns.
27 October 2015
Address Contents
00
14
01
02
02
34
03
17
04
C0
05
00
Brookshire, Section 2.3
18
Program to Add Two Values
1.
2.
3.
4.
5.
Get the first value from memory and
place it in a register S.
Get the second value from memory
and place it in another register T.
Add the contents of S, T and place the
result in a register R.
Store the result in R in memory
Stop
27 October 2015
Brookshear, Section 2.3
19
Encoded Program
1.
2.
3.
4.
5.
156C. Load register 5 with the contents of
memory cell 6C.
166D. Load register 6 with the contents of
memory cell 6D
5056. Add (2s comp) contents of registers
5, 6. Put result in register 0.
306E. Store the contents of Register 0 at
memory cell 6E.
C000. Halt.
27 October 2015
Brookshear, Section 2.3
20
Without Instruction B
 A program containing n instructions
would run for n-1 machine cycles.
 The program would be unable to
respond to changes in the data.
27 October 2015
Birkbeck College, U. London
21
Fibonacci Numbers
 0,1,1,2,3,5,8,13,21,34,55, …
 N(1)=0, N(2)=1
 N(i+1)=N(i)+N(i-1) for i=2,3,4, …
27 October 2015
Birkbeck College, U. London
22
Program to Find the 10th Fibonacci Number
Address Instruction Comment
20
2000 // load register 0 with 0
22
2100 // load register 1 with 0
24
2201 // load register 2 with 1
26
2408 // load register 4 with 8
28
25FF // load register 5 with -1 (Two’s Comp)
R0
00
27 October 2015
R1
00
R2
01
R3
**
Birkbeck College, U. London
R4
08
R5
FF
23
Program to Find the 10th Fibonacci Number
Address Instruction Comment
2A
3C
2E
30
32
34
36
5312
4021
4032
5445
B436
B02A
C000
27 October 2015
// Add contents of R1, R2. Put result in R3
// Move bit pattern in R2 to R1
// Move bit pattern in R3 to R2
// Add contents of R4, R5. Put result in R4
// If contents R4=contents R0, go to 36
// If contents R0=contents R0, go to 2A
// Halt. Result is in R2.
Birkbeck College, U. London
24
Assembly Language

Mnemonic system for representing
machine language
Machine language
Assembly language
156C
166D
5056
306E
C000
LD R5, Price
LD R6, ShippingCharge
ADDI R0, R5, R6
St R0, TotalCost
HLT
27 October 2015
Brookshear, Section 6.1
25